Commit Graph
49 Commits
Author SHA1 Message Date
octagonal da6e1ea7b0 Simple mandelbrot in rust 2025-11-25 17:16:32 +01:00
octagonal c0b4311458 Ups frequency to 80Mhz : unstable behaviour 2025-11-16 16:45:00 +01:00
octagonal dbe0a488f3 Corrects Clint module, and adds rust clint debugger 2025-11-16 15:24:34 +01:00
octagonal 4955f9b952 Gets rust running rv64iM 2025-11-16 12:19:49 +01:00
octagonal 674c399ef6 Adds sample rust program 2025-11-15 02:11:00 +01:00
octagonal cfce066cd7 Modifies test slightly because now RAM is relocated to 0x10000 2025-11-15 01:26:49 +01:00
octagonal e35f2a4242 Corrects critical mistake where core tried to bypass even if previous instruction did not write-back 2025-11-15 00:57:59 +01:00
octagonal 0c377a1380 Adds a way to simulate the programs with spike, to compare PCs and debug 2025-11-15 00:57:30 +01:00
surv e55c3fde14 Reduces LUT needed by mul extension 2025-11-14 19:08:41 +01:00
octagonal ca03b29774 Rust character drawing 2025-11-14 09:58:58 +01:00
octagonal d8596b2247 Rust character drawing 2025-11-14 09:57:42 +01:00
surv f5d8c77d06 Improves test for jumps 2025-11-14 08:55:07 +01:00
surv 823f4ed43c Merge branch 'rust' 2025-11-13 10:41:19 +01:00
surv 780da5b6d2 Merge branch 'main' into rv64im 2025-11-13 10:28:22 +01:00
surv 7bc23ce211 Starts adding fontplate for VGA 2025-11-13 10:26:37 +01:00
octagonal 470445c441 Merge branch 'rv64i' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa into rv64i 2025-11-13 09:49:37 +01:00
octagonal 030149cbea Rv64i : passing test 2025-11-13 09:49:18 +01:00
surv c8cd44974f Fixs JALR instruction 2025-11-13 09:01:54 +01:00
surv 3044a54a09 Add registers in rust 2025-11-12 23:51:16 +01:00
surv 8326c1f169 Starts adding rust in the toolchain 2025-11-12 22:05:25 +01:00
octagonal 7bb8b993ae Implements (mostly untested) rv64i) 2025-11-12 18:02:14 +01:00
surv 02fcf5ee2c Merge branch 'rv64i' into rv64im 2025-11-12 12:22:34 +01:00
octagonal 992cf37b92 Moves control unit ops to separate files 2025-11-12 11:53:28 +01:00
surv cfacd6a9fc rv64im: passing tests 2025-11-12 11:50:09 +01:00
surv 7a1221b16e Merge branch 'rv64i' into rv64im 2025-11-11 19:17:46 +01:00
surv 8cff4de02e Adds extension M instructions: not tested 2025-11-11 13:10:19 +01:00
octagonal 4c967431ed Adds a test for load immediate (li) pseudo instruction
This makes sure the other tests can build upon a sane base
2025-11-11 11:05:05 +01:00
octagonal 297562766c Adds addiw instruction, all tests passing 2025-11-10 22:07:15 +01:00
octagonal 9daa296892 Lays groundword for Rv64i extension
Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory
2025-11-10 16:38:40 +01:00
octagonal 03e315903e Implements sub: passing tests 2025-11-09 18:33:12 +01:00
surv 441f665d34 Stage 12: passing tests 2025-11-09 18:23:24 +01:00
octagonal 603a1ac54a Stage 11: Passing tests 2025-11-09 17:48:18 +01:00
surv 4018f69f65 Stage 10: passing tests 2025-11-09 15:35:42 +01:00
surv ec60da2be3 Merges upstream 2025-11-08 18:57:55 +01:00
surv 60d57b69bf Stage 10: test not passing 2025-11-08 18:56:19 +01:00
octagonal 036f432d76 Stage 9: Full implemntation + passing tests 2025-11-07 18:03:45 +01:00
octagonal e83e7c11c1 Stage 8: all tests passing 2025-11-07 15:27:15 +01:00
octagonal c88662403e Attempts to implement jalr, test not passing 2025-11-07 13:37:46 +01:00
surv cbf7ec9ad3 Add jal instruction 2025-11-07 11:51:33 +01:00
octagonal c2c16d9672 Stage 7: Register to register operations, all tests passing 2025-11-06 19:02:42 +01:00
surv 37435c6677 Add tests for stage 7 2025-11-06 18:52:31 +01:00
octagonal 1c829366de Implements stage 6: tests passing 2025-11-06 18:38:32 +01:00
surv 5f696dc8e7 Refactor tests 2025-11-06 16:34:17 +01:00
octagonal 2779471523 Stage 6: implementation, untested 2025-11-06 16:18:01 +01:00
surv 1462563e39 Implements stage 5 2025-11-05 20:01:41 +01:00
octagonal 5df85799ef Stage 4: Implements auipc 2025-11-05 18:40:27 +01:00
Frederic Petrot fa03cb14d8 Changement de la multiplication dans invaders
Afin d'éviter les problèmes d'édition de liens avec l'option -Os sous gcc-15
2025-11-04 22:29:10 +01:00
Olivier Muller cb3dddc77a ajout stage1 2025-11-04 14:29:47 +01:00
Olivier Muller ff440776bb Squelette du projet 2025-11-03 11:00:11 +01:00