Merge branch 'rv64i' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa into rv64i

bench/tests/op/jalr.s

@@ -13,3 +13,4 @@ step2:
     jalr x0, 4(x2) # return to step1, but 1 further
 finish:
     nop
+    addi x31, x0, 0x0AB # This instruction should never be executed

src/main/scala/projet/ControlUnit.scala

@@ -54,7 +54,7 @@ class CUInterface extends Bundle {
     val mux_regpc_executepc = Output(Bool())
 
     // Selects pc adder or write back for pc write
-    val mux_pcadder_writeback = Output(Bool())
+    val mux_pcadder_jalrwriteback = Output(Bool())
 
     // Selects pc or write back for register write
     val mux_writeback_pc = Output(Bool())
@@ -137,7 +137,7 @@ class ControlUnit() extends Module {
     io.mux_incrpc4_imm := true.B;
     io.mux_regpc_executepc := true.B;
     io.mux_writeback_pc := true.B;
-    io.mux_pcadder_writeback := true.B;
+    io.mux_pcadder_jalrwriteback := true.B;
     io.mux_executeout_dout := true.B;
 
     // Decode instruction
@@ -175,7 +175,7 @@ class ControlUnit() extends Module {
             io.is_jump := true.B
             io.mux_incrpc4_imm := false.B; // Send the immediate in PC
             io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
-            io.mux_pcadder_writeback := true.B;
+            io.mux_pcadder_jalrwriteback := true.B;
             io.optype := OpType.J
         }
 
@@ -190,7 +190,7 @@ class ControlUnit() extends Module {
             io.mux_regb_imm := false.B; // Send imm to ALU B
 
             io.mux_alu_imm := true.B; // Send alu out to write back line
-            io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
+            io.mux_pcadder_jalrwriteback := false.B; // Set pc to writeback dest
             io.optype := OpType.I
         }
 

src/main/scala/projet/Rv64i.scala

@@ -119,6 +119,8 @@ class Rv64i(sim: Boolean = true) extends Module {
     // Select what to send on writeback line
     val execute_out = Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
     reg_execute_out := execute_out;
+    // Jalr line is directly the execute output
+    val jalr_line = execute_out
 
     reg_mux_executeout_dout := control_unit.io.mux_executeout_dout;
 
@@ -131,9 +133,9 @@ class Rv64i(sim: Boolean = true) extends Module {
 
     // Writeback pipelining registers
     reg_pc := Mux(
-        Delay.Delay(control_unit.io.mux_pcadder_writeback, 1, true.B),
+        control_unit.io.mux_pcadder_jalrwriteback,
         pc_adder_out,
-        writeback_line
+        jalr_line
     );
 
     dmem.io.data_in := rs2_data

src/main/scala/projet/op/OpBranch.scala

@@ -78,7 +78,7 @@ object OpBranch {
 
         // Branch if comparison is successful
         when(branch) {
-            io.mux_pcadder_writeback := true.B;
+            io.mux_pcadder_jalrwriteback := true.B;
             io.mux_incrpc4_imm := false.B;
             io.mux_regpc_executepc := false.B;
             io.is_jump := true.B;