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Ups frequency to 80Mhz : unstable behaviour

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This commit is contained in:
Albin Chaboissier
2025-11-16 16:45:00 +01:00
parent dbe0a488f3
commit c0b4311458
5 changed files with 181 additions and 100 deletions
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2
bench/programs_rust/hello-rust/src/main.rs
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@@ -24,7 +24,7 @@ pub extern "C" fn main() -> !
let clint_time: *mut u64 = 0x0200bff8 as *mut u64;
let clocks = *clint_time;
let seconds = clocks / (125_000_000 / 2);
let seconds = clocks / 80_000_000;
VGA::draw_string(100, 10, "CLint:", BLUE);
VGA::draw_u64(150, 10, clocks, BLUE, BLACK);
VGA::draw_string(100, 23, "(s)", BLUE);

63
src/main/resources/vsrc/clk_wiz.v
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@@ -1,5 +1,5 @@
// file: design_1_clk_wiz_0_0.v
// file: clk_wiz_0.v
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
@@ -53,17 +53,17 @@
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1__10.00000______0.000______50.0______197.700_____96.948
// clk_out1__80.00000______0.000______50.0______130.375_____96.948
// clk_out2__125.00000______0.000______50.0______119.348_____96.948
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________125.000____________0.010
// __primary_____________125____________0.010
`timescale 1ps/1ps
module clk_wiz
module clk_wiz
(// Clock in ports
// Clock out ports
@@ -76,12 +76,15 @@ module clk_wiz
);
// Input buffering
//------------------------------------
wire clk_in1_design_1_clk_wiz_0_0;
wire clk_in2_design_1_clk_wiz_0_0;
wire clk_in1_clk_wiz_0;
wire clk_in2_clk_wiz_0;
IBUF clkin1_ibufg
(.O (clk_in1_design_1_clk_wiz_0_0),
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
@@ -89,20 +92,20 @@ wire clk_in2_design_1_clk_wiz_0_0;
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_design_1_clk_wiz_0_0;
wire clk_out2_design_1_clk_wiz_0_0;
wire clk_out3_design_1_clk_wiz_0_0;
wire clk_out4_design_1_clk_wiz_0_0;
wire clk_out5_design_1_clk_wiz_0_0;
wire clk_out6_design_1_clk_wiz_0_0;
wire clk_out7_design_1_clk_wiz_0_0;
wire clk_out1_clk_wiz_0;
wire clk_out2_clk_wiz_0;
wire clk_out3_clk_wiz_0;
wire clk_out4_clk_wiz_0;
wire clk_out5_clk_wiz_0;
wire clk_out6_clk_wiz_0;
wire clk_out7_clk_wiz_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_design_1_clk_wiz_0_0;
wire clkfbout_buf_design_1_clk_wiz_0_0;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
@@ -126,7 +129,7 @@ wire clk_in2_design_1_clk_wiz_0_0;
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (100.000),
.CLKOUT0_DIVIDE_F (12.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
@@ -138,11 +141,11 @@ wire clk_in2_design_1_clk_wiz_0_0;
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_design_1_clk_wiz_0_0),
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_design_1_clk_wiz_0_0),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_design_1_clk_wiz_0_0),
.CLKOUT1 (clk_out2_clk_wiz_0),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
@@ -152,8 +155,8 @@ wire clk_in2_design_1_clk_wiz_0_0;
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_design_1_clk_wiz_0_0),
.CLKIN1 (clk_in1_design_1_clk_wiz_0_0),
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
@@ -185,16 +188,24 @@ wire clk_in2_design_1_clk_wiz_0_0;
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_design_1_clk_wiz_0_0),
.I (clkfbout_design_1_clk_wiz_0_0));
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_design_1_clk_wiz_0_0));
.I (clk_out1_clk_wiz_0));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_design_1_clk_wiz_0_0));
.I (clk_out2_clk_wiz_0));
endmodule

145
src/main/scala/projet/Alu.scala
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@@ -65,19 +65,19 @@ class Alu extends Module {
val in_computation = RegInit(false.B)
// Division
val divider = Module(new Divider(64, Constants.DIVISION_CYCLES_COUNT))
divider.io.word_mode := io.word_mode
divider.io.dividend := op_a_unsigned
divider.io.divisor := op_b_unsigned
divider.io.start := false.B
def div_by_zero() = {
when(io.word_mode) {
out := (-1).S(32.W).asUInt
}.otherwise {
out := (-1).S(64.W).asUInt
}
}
// // Division
// val divider = Module(new Divider(64, Constants.DIVISION_CYCLES_COUNT))
// divider.io.word_mode := io.word_mode
// divider.io.dividend := op_a_unsigned
// divider.io.divisor := op_b_unsigned
// divider.io.start := false.B
// def div_by_zero() = {
// when(io.word_mode) {
// out := (-1).S(32.W).asUInt
// }.otherwise {
// out := (-1).S(64.W).asUInt
// }
// }
// Multiplication
val multiplication_res = op_a * op_b // Mul non signée
@@ -123,54 +123,54 @@ class Alu extends Module {
out := multiplication_high;
}
is(Div) {
when(op_b === 0.U) {
div_by_zero()
}.elsewhen(op_a_sign ^ op_b_sign) {
out := Utils.two_complement(divider.io.quotient, io.word_mode)
}.otherwise {
out := divider.io.quotient
}
}
is(Divu) {
divider.io.dividend := op_a
divider.io.divisor := op_b
when(op_b === 0.U) {
div_by_zero()
}.otherwise { out := divider.io.quotient; }
}
is(Rem) {
when(op_b === 0.U) {
out := op_a
}.elsewhen(
op_a_sign && !op_b_sign && divider.io.remainder =/= 0.U
) {
out := op_b - divider.io.remainder
}.elsewhen(
!op_a_sign && op_b_sign && divider.io.remainder =/= 0.U
) {
out := Utils.two_complement(
Utils.two_complement(op_b) - divider.io.remainder,
io.word_mode
)
}.elsewhen(op_a_sign && op_b_sign) {
out := Utils.two_complement(divider.io.remainder, io.word_mode)
}.otherwise {
out := divider.io.remainder
}
}
is(Remu) {
divider.io.dividend := op_a
divider.io.divisor := op_b
when(op_b === 0.U) {
out := op_a
}.otherwise {
out := divider.io.remainder
}
}
// is(Div) {
// when(op_b === 0.U) {
// div_by_zero()
// }.elsewhen(op_a_sign ^ op_b_sign) {
// out := Utils.two_complement(divider.io.quotient, io.word_mode)
// }.otherwise {
// out := divider.io.quotient
// }
// }
//
// is(Divu) {
// divider.io.dividend := op_a
// divider.io.divisor := op_b
// when(op_b === 0.U) {
// div_by_zero()
// }.otherwise { out := divider.io.quotient; }
// }
//
// is(Rem) {
// when(op_b === 0.U) {
// out := op_a
// }.elsewhen(
// op_a_sign && !op_b_sign && divider.io.remainder =/= 0.U
// ) {
// out := op_b - divider.io.remainder
// }.elsewhen(
// !op_a_sign && op_b_sign && divider.io.remainder =/= 0.U
// ) {
// out := Utils.two_complement(
// Utils.two_complement(op_b) - divider.io.remainder,
// io.word_mode
// )
// }.elsewhen(op_a_sign && op_b_sign) {
// out := Utils.two_complement(divider.io.remainder, io.word_mode)
// }.otherwise {
// out := divider.io.remainder
// }
// }
//
// is(Remu) {
// divider.io.dividend := op_a
// divider.io.divisor := op_b
// when(op_b === 0.U) {
// out := op_a
// }.otherwise {
// out := divider.io.remainder
// }
// }
is(And) {
out := op_a & op_b;
@@ -231,17 +231,18 @@ class Alu extends Module {
}
}
switch(io.opcode) {
is(Div, Divu, Rem, Remu) {
when(!in_computation) {
divider.io.start := true.B
in_computation := true.B
}.elsewhen(divider.io.ready) {
io.should_stop_stall := true.B
in_computation := false.B
}
}
}
// switch(io.opcode) {
// is(Div, Divu, Rem, Remu) {
// when(!in_computation) {
// divider.io.start := true.B
// in_computation := true.B
// }.elsewhen(divider.io.ready) {
// io.should_stop_stall := true.B
// in_computation := false.B
// }
// }
// }
//
// Special overflow cases for Div and Rem
when(

2
src/main/scala/projet/Constants.scala
View File

@@ -1,5 +1,5 @@
package projet
object Constants {
def DIVISION_CYCLES_COUNT = 8
def DIVISION_CYCLES_COUNT = 32
}

69
tight_setup_hold_pins.txt Normal file
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@@ -0,0 +1,69 @@
+====================+====================+==============================+
| Launch Setup Clock | Launch Hold Clock | Pin |
+====================+====================+==============================+
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[58]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[52]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[32]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[61]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[54]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[17]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[42]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[11]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[8]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[36]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[19]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[60]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[51]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[41]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[50]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[37]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[1]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[62]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[38]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[10]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[14]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[63]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[28]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[9]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[58]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[61]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[60]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[52]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[45]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[44]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[41]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[40]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[37]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[36]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[33]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[32]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[28]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[25]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[21]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[17]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[16]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[13]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[9]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[8]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[5]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[4]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[1]/D |
+--------------------+--------------------+------------------------------+