octagonal
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470445c441
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Merge branch 'rv64i' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa into rv64i
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2025-11-13 09:49:37 +01:00 |
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octagonal
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030149cbea
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Rv64i : passing test
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2025-11-13 09:49:18 +01:00 |
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octagonal
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7bb8b993ae
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Implements (mostly untested) rv64i)
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2025-11-12 18:02:14 +01:00 |
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octagonal
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8ac17f20fe
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Cleans up control unit
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2025-11-12 11:58:49 +01:00 |
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octagonal
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992cf37b92
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Moves control unit ops to separate files
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2025-11-12 11:53:28 +01:00 |
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octagonal
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4c967431ed
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Adds a test for load immediate (li) pseudo instruction
This makes sure the other tests can build upon a sane base
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2025-11-11 11:05:05 +01:00 |
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octagonal
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297562766c
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Adds addiw instruction, all tests passing
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2025-11-10 22:07:15 +01:00 |
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octagonal
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9daa296892
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Lays groundword for Rv64i extension
Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory
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2025-11-10 16:38:40 +01:00 |
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octagonal
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03e315903e
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Implements sub: passing tests
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2025-11-09 18:33:12 +01:00 |
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octagonal
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603a1ac54a
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Stage 11: Passing tests
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2025-11-09 17:48:18 +01:00 |
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octagonal
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036f432d76
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Stage 9: Full implemntation + passing tests
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2025-11-07 18:03:45 +01:00 |
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octagonal
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2117f8155e
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Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa
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2025-11-07 17:04:37 +01:00 |
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octagonal
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a897778605
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Modifies alu for branching instructions
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2025-11-07 17:04:05 +01:00 |
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octagonal
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ea211d8a74
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Reduces CPU cycles to 2 clock cycles for faster testing/simulation
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2025-11-07 15:34:08 +01:00 |
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octagonal
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e83e7c11c1
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Stage 8: all tests passing
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2025-11-07 15:27:15 +01:00 |
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octagonal
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c88662403e
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Attempts to implement jalr, test not passing
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2025-11-07 13:37:46 +01:00 |
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octagonal
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3828850dd6
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Use nproc for parallel testing
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2025-11-07 12:11:29 +01:00 |
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octagonal
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3761077b84
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Merges build.sc
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2025-11-07 12:03:27 +01:00 |
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octagonal
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479526a0fb
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Adds parallel testing
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2025-11-07 12:02:17 +01:00 |
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octagonal
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0e991583b9
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Changes binary notation in ControlUnit to make formatter happy
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2025-11-07 10:41:09 +01:00 |
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octagonal
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1adf33810f
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Add .csv to .gitignore
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2025-11-07 10:38:39 +01:00 |
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octagonal
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47d290c5c2
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Adds more vivado logs to .gitignore
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2025-11-07 10:37:44 +01:00 |
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octagonal
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a9790209fa
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Adds .rpt from gitignore to remove vivado logs
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2025-11-07 10:35:57 +01:00 |
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octagonal
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c2c16d9672
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Stage 7: Register to register operations, all tests passing
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2025-11-06 19:02:42 +01:00 |
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octagonal
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1c829366de
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Implements stage 6: tests passing
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2025-11-06 18:38:32 +01:00 |
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octagonal
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2779471523
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Stage 6: implementation, untested
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2025-11-06 16:18:01 +01:00 |
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octagonal
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5df85799ef
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Stage 4: Implements auipc
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2025-11-05 18:40:27 +01:00 |
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octagonal
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7956338fbc
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Stage 1 + removes hardcoded paths
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2025-11-04 15:41:33 +01:00 |
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octagonal
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5fa7f8949f
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Merge branch 'main' of gitlab.ensimag.fr:archi/FMN_projet
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2025-11-04 14:47:13 +01:00 |
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