Files
fmn_processor/bench/tests/op/divw.s

61 lines
1.4 KiB
ArmAsm

.text
_start:
li x2, 0xdead0 # 912080
li x3, 0x1234 # 4660
li x4, 1 # 1
li x5, -123456 # -123456
li x6, 0xdead0 # duplicate of x2
li x7, -765432 # -765432
li x8, 123456 # 123456
li x9, -234567 # -234567
li x10, 0x7fffffff # max positive 32b
li x11, 0x80000000 # min negative 32b
# 1. DIVW : a / 1
divw x31, x2, x4
# expected: 000000000000dead0
# 2. DIVW : a / a
divw x31, x2, x6
# expected: 0000000000000001
# 3. DIVW : negative / positive
divw x31, x5, x8
# expected: ffffffffffffffff
# 4. DIVW : negative / positive
divw x31, x7, x8
# expected: fffffffffffffffa
# 5. DIVW : positive / negative
divw x31, x8, x7
# expected: 0000000000000000
# 6. DIVW : negative / negative
divw x31, x7, x9
# expected: 0000000000000003
# 7. DIVW : max / 2
li x12, 2
divw x31, x10, x12
# expected: 000000003fffffff
# 8. DIVW : min / -1
li x12, -1 # -1
divw x31, x11, x12
# expected: ffffffff80000000
# 9. DIVW : min / 1
divw x31, x11, x4
# expected: ffffffff80000000
# 10. DIVW : 0 / any
divw x31, x0, x2
# expected: 0000000000000000
# 11. DIVW : any / 0
divw x31, x2, x0
# expected: ffffffffffffffff
divw x31, x7, x0
# expected: ffffffffffffffff