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cfacd6a9fc
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rv64im: passing tests
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2025-11-12 11:50:09 +01:00 |
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7a1221b16e
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Merge branch 'rv64i' into rv64im
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2025-11-11 19:17:46 +01:00 |
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8cff4de02e
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Adds extension M instructions: not tested
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2025-11-11 13:10:19 +01:00 |
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297562766c
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Adds addiw instruction, all tests passing
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2025-11-10 22:07:15 +01:00 |
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03e315903e
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Implements sub: passing tests
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2025-11-09 18:33:12 +01:00 |
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603a1ac54a
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Stage 11: Passing tests
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2025-11-09 17:48:18 +01:00 |
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4018f69f65
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Stage 10: passing tests
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2025-11-09 15:35:42 +01:00 |
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60d57b69bf
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Stage 10: test not passing
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2025-11-08 18:56:19 +01:00 |
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43a11c865b
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Stage 10: not tested
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2025-11-07 18:37:58 +01:00 |
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036f432d76
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Stage 9: Full implemntation + passing tests
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2025-11-07 18:03:45 +01:00 |
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e83e7c11c1
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Stage 8: all tests passing
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2025-11-07 15:27:15 +01:00 |
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c88662403e
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Attempts to implement jalr, test not passing
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2025-11-07 13:37:46 +01:00 |
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99c5e0c78c
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Changes binary notation in ControlUnit to make formatter happy
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2025-11-07 11:53:09 +01:00 |
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9c5313522d
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Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa
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2025-11-07 11:51:43 +01:00 |
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cbf7ec9ad3
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Add jal instruction
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2025-11-07 11:51:33 +01:00 |
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0e991583b9
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Changes binary notation in ControlUnit to make formatter happy
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2025-11-07 10:41:09 +01:00 |
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c2c16d9672
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Stage 7: Register to register operations, all tests passing
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2025-11-06 19:02:42 +01:00 |
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1c829366de
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Implements stage 6: tests passing
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2025-11-06 18:38:32 +01:00 |
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2779471523
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Stage 6: implementation, untested
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2025-11-06 16:18:01 +01:00 |
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1462563e39
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Implements stage 5
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2025-11-05 20:01:41 +01:00 |
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5df85799ef
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Stage 4: Implements auipc
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2025-11-05 18:40:27 +01:00 |
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3870e05613
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Implements stage 3
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2025-11-05 17:23:33 +01:00 |
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