60 lines
1.3 KiB
Scala
60 lines
1.3 KiB
Scala
package projet
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import chisel3._
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import chisel3.util.switch
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import chisel3.util.is
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class CUInterface extends Bundle {
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val instruction = Input(UInt(32.W))
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val reg_file_we = Output(Bool())
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val alu_opcode = Output(AluOpCode())
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val optype = Output(OpType())
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val mux_alu_imm = Output(Bool())
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val mux_rega_pc = Output(Bool())
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}
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object OpType extends ChiselEnum {
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val U, I = Value
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}
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object OpCode extends ChiselEnum {
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val LUI = 0b0110111.U
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val AUIPC = 0b0010111.U
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val ADDI = 0b0010011.U
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}
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class ControlUnit() extends Module {
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import OpCode._
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val io = IO(new CUInterface())
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io.reg_file_we := false.B
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io.alu_opcode := AluOpCode.Add
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io.optype := OpType.U
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io.mux_alu_imm := true.B;
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io.mux_rega_pc := true.B;
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switch(io.instruction(6, 0)) {
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// U instructions
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is(LUI) {
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io.reg_file_we := true.B
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io.mux_alu_imm := false.B
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io.optype := OpType.U
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}
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is(AUIPC) {
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io.alu_opcode := AluOpCode.Add
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io.reg_file_we := true.B
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io.mux_rega_pc := false.B
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io.optype := OpType.U
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}
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// I instructions
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is(ADDI) {
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io.alu_opcode := AluOpCode.Add
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io.reg_file_we := true.B
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io.optype := OpType.I
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}
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}
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}
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