package projet

import chisel3._
import chisel3.util.switch
import chisel3.util.is

class CUInterface extends Bundle {
    val instruction = Input(UInt(32.W))
    val reg_file_we = Output(Bool())
    val alu_opcode = Output(AluOpCode())
    val optype = Output(OpType())

    val mux_alu_imm = Output(Bool())
    val mux_rega_pc = Output(Bool())
}

object OpType extends ChiselEnum {
    val U, I = Value
}

object OpCode extends ChiselEnum {
    val LUI = 0b0110111.U
    val AUIPC = 0b0010111.U
    val ADDI = 0b0010011.U
}

class ControlUnit() extends Module {
    import OpCode._

    val io = IO(new CUInterface())

    io.reg_file_we := false.B
    io.alu_opcode := AluOpCode.Add
    io.optype := OpType.U
    io.mux_alu_imm := true.B;
    io.mux_rega_pc := true.B;
    switch(io.instruction(6, 0)) {

        // U instructions
        is(LUI) {
            io.reg_file_we := true.B
            io.mux_alu_imm := false.B
            io.optype := OpType.U
        }
        is(AUIPC) {
            io.alu_opcode := AluOpCode.Add 
            io.reg_file_we := true.B
            io.mux_rega_pc := false.B
            io.optype := OpType.U
        }

        // I instructions
        is(ADDI) {
            io.alu_opcode := AluOpCode.Add 
            io.reg_file_we := true.B
            io.optype := OpType.I
        }
    }
}