Commit Graph

71 Commits

Author SHA1 Message Date
84569017c8 Corrects critical mistake in JAL, corrects VgaIp 2025-11-13 16:53:04 +01:00
1d0aa7db4b Fixs merge conflict with word mode 2025-11-13 10:35:17 +01:00
780da5b6d2 Merge branch 'main' into rv64im 2025-11-13 10:28:22 +01:00
355c700efe Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-13 10:13:53 +01:00
3958a6ad8f Adds verilator flags (seemingly not working) 2025-11-13 10:13:23 +01:00
470445c441 Merge branch 'rv64i' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa into rv64i 2025-11-13 09:49:37 +01:00
030149cbea Rv64i : passing test 2025-11-13 09:49:18 +01:00
c8cd44974f Fixs JALR instruction 2025-11-13 09:01:54 +01:00
7bb8b993ae Implements (mostly untested) rv64i) 2025-11-12 18:02:14 +01:00
02fcf5ee2c Merge branch 'rv64i' into rv64im 2025-11-12 12:22:34 +01:00
8ac17f20fe Cleans up control unit 2025-11-12 11:58:49 +01:00
992cf37b92 Moves control unit ops to separate files 2025-11-12 11:53:28 +01:00
cfacd6a9fc rv64im: passing tests 2025-11-12 11:50:09 +01:00
7a1221b16e Merge branch 'rv64i' into rv64im 2025-11-11 19:17:46 +01:00
f9cbcaf20f Add BSwitch macro and update gtkwave config 2025-11-11 19:12:12 +01:00
8cff4de02e Adds extension M instructions: not tested 2025-11-11 13:10:19 +01:00
4c967431ed Adds a test for load immediate (li) pseudo instruction
This makes sure the other tests can build upon a sane base
2025-11-11 11:05:05 +01:00
297562766c Adds addiw instruction, all tests passing 2025-11-10 22:07:15 +01:00
9daa296892 Lays groundword for Rv64i extension
Some base files had to be modified to support 64-bit architecture
as well as the Makefile to load 64-bit words into memory
2025-11-10 16:38:40 +01:00
d225894765 Required values in tests can be splitted on several lines 2025-11-10 11:19:40 +01:00
cbfd806444 Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-09 19:47:51 +01:00
15d9707571 Writes reg(31) on x31 when running on the board 2025-11-09 19:47:05 +01:00
03e315903e Implements sub: passing tests 2025-11-09 18:33:12 +01:00
441f665d34 Stage 12: passing tests 2025-11-09 18:23:24 +01:00
603a1ac54a Stage 11: Passing tests 2025-11-09 17:48:18 +01:00
4018f69f65 Stage 10: passing tests 2025-11-09 15:35:42 +01:00
5c05d0b3e5 Fix makefile 2025-11-09 13:45:44 +01:00
ec60da2be3 Merges upstream 2025-11-08 18:57:55 +01:00
60d57b69bf Stage 10: test not passing 2025-11-08 18:56:19 +01:00
43a11c865b Stage 10: not tested 2025-11-07 18:37:58 +01:00
036f432d76 Stage 9: Full implemntation + passing tests 2025-11-07 18:03:45 +01:00
2117f8155e Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-07 17:04:37 +01:00
a897778605 Modifies alu for branching instructions 2025-11-07 17:04:05 +01:00
6dd2cf0298 Refactor Spec files 2025-11-07 15:54:04 +01:00
ea211d8a74 Reduces CPU cycles to 2 clock cycles for faster testing/simulation 2025-11-07 15:34:08 +01:00
e83e7c11c1 Stage 8: all tests passing 2025-11-07 15:27:15 +01:00
c88662403e Attempts to implement jalr, test not passing 2025-11-07 13:37:46 +01:00
3828850dd6 Use nproc for parallel testing 2025-11-07 12:11:29 +01:00
3761077b84 Merges build.sc 2025-11-07 12:03:27 +01:00
479526a0fb Adds parallel testing 2025-11-07 12:02:17 +01:00
99c5e0c78c Changes binary notation in ControlUnit to make formatter happy 2025-11-07 11:53:09 +01:00
9c5313522d Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-07 11:51:43 +01:00
cbf7ec9ad3 Add jal instruction 2025-11-07 11:51:33 +01:00
0e991583b9 Changes binary notation in ControlUnit to make formatter happy 2025-11-07 10:41:09 +01:00
1adf33810f Add .csv to .gitignore 2025-11-07 10:38:39 +01:00
47d290c5c2 Adds more vivado logs to .gitignore 2025-11-07 10:37:44 +01:00
a9790209fa Adds .rpt from gitignore to remove vivado logs 2025-11-07 10:35:57 +01:00
c2c16d9672 Stage 7: Register to register operations, all tests passing 2025-11-06 19:02:42 +01:00
37435c6677 Add tests for stage 7 2025-11-06 18:52:31 +01:00
1c829366de Implements stage 6: tests passing 2025-11-06 18:38:32 +01:00