Squelette du projet
This commit is contained in:
Olivier Muller
147
common/ZzTop.xdc
Normal file
147
common/ZzTop.xdc
Normal file
@@ -0,0 +1,147 @@
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## This file is a general .xdc for the ZYBO Rev B board
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## To use it in a project:
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## - uncomment the lines corresponding to used pins
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## - rename the used signals according to the project
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# Clock signal
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set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clock }]; #IO_L11P_T1_SRCC_35 Sch=sysclk
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create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clock }];
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# Switches
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set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { io_switch[0] }]; #IO_L19N_T3_VREF_35 Sch=SW0
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set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { io_switch[1] }]; #IO_L24P_T3_34 Sch=SW1
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set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { io_switch[2] }]; #IO_L4N_T0_34 Sch=SW2
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set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { io_switch[3] }]; #IO_L9P_T1_DQS_34 Sch=SW3
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# Buttons
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set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { io_push[0] }]; #IO_L20N_T3_34 Sch=BTN0
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set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { io_push[1] }]; #IO_L24N_T3_34 Sch=BTN1
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set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { io_push[2] }]; #IO_L18P_T2_34 Sch=BTN2
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set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { reset }]; #IO_L7P_T1_34 Sch=BTN3
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# LEDs
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set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_led[0] }]; #IO_L23P_T3_35 Sch=LED0
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set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { io_led[1] }]; #IO_L23N_T3_35 Sch=LED1
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set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { io_led[2] }]; #IO_0_35 Sch=LED2
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set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { io_led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3
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##I2S Audio Codec
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#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
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#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_25_34 Sch=AC_MCLK
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#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ac_muten }]; #IO_L23N_T3_34 Sch=AC_MUTEN
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#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ac_pbdat }]; #IO_L8P_T1_AD10P_35 Sch=AC_PBDAT
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#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ac_pblrc }]; #IO_L11N_T1_SRCC_35 Sch=AC_PBLRC
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#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { ac_recdat }]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
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#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ac_reclrc }]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC
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##Audio Codec/external EEPROM IIC bus
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#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ac_scl }]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
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#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ac_sda }]; #IO_L23P_T3_34 Sch=AC_SDA
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##Additional Ethernet signals
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#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_int_b }]; #IO_L6P_T0_35 Sch=ETH_INT_B
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#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ETH_RST_B
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##HDMI Signals
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#set_property -dict { PACKAGE_PIN H17 IOSTANDARD TMDS_33 } [get_ports { hdmi_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=HDMI_CLK_N
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#set_property -dict { PACKAGE_PIN H16 IOSTANDARD TMDS_33 } [get_ports { hdmi_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=HDMI_CLK_P
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#set_property -dict { PACKAGE_PIN D20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[0] }]; #IO_L4N_T0_35 Sch=HDMI_D0_N
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#set_property -dict { PACKAGE_PIN D19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[0] }]; #IO_L4P_T0_35 Sch=HDMI_D0_P
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#set_property -dict { PACKAGE_PIN B20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[1] }]; #IO_L1N_T0_AD0N_35 Sch=HDMI_D1_N
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#set_property -dict { PACKAGE_PIN C20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[1] }]; #IO_L1P_T0_AD0P_35 Sch=HDMI_D1_P
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#set_property -dict { PACKAGE_PIN A20 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_n[2] }]; #IO_L2N_T0_AD8N_35 Sch=HDMI_D2_N
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#set_property -dict { PACKAGE_PIN B19 IOSTANDARD TMDS_33 } [get_ports { hdmi_d_p[2] }]; #IO_L2P_T0_AD8P_35 Sch=HDMI_D2_P
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#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_cec }]; #IO_L5N_T0_AD9N_35 Sch=HDMI_CEC
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#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_hpd }]; #IO_L5P_T0_AD9P_35 Sch=HDMI_HPD
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#set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_en }]; #IO_L6N_T0_VREF_35 Sch=HDMI_OUT_EN
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#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_scl }]; #IO_L16P_T2_35 Sch=HDMI_SCL
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#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_sda }]; #IO_L16N_T2_35 Sch=HDMI_SDA
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##Pmod Header JA (XADC)
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#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ja_p[0] }]; #IO_L21P_T3_DQS_AD14P_35 Sch=JA1_R_p
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#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[1] }]; #IO_L22P_T3_AD7P_35 Sch=JA2_R_P
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#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja_p[2] }]; #IO_L24P_T3_AD15P_35 Sch=JA3_R_P
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#set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ja_p[3] }]; #IO_L20P_T3_AD6P_35 Sch=JA4_R_P
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#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[0] }]; #IO_L21N_T3_DQS_AD14N_35 Sch=JA1_R_N
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#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { ja_n[1] }]; #IO_L22N_T3_AD7N_35 Sch=JA2_R_N
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#set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ja_n[2] }]; #IO_L24N_T3_AD15N_35 Sch=JA3_R_N
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#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ja_n[3] }]; #IO_L20N_T3_AD6N_35 Sch=JA4_R_N
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##Pmod Header JB
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#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[0] }]; #IO_L15P_T2_DQS_34 Sch=JB1_p
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#set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[0] }]; #IO_L15N_T2_DQS_34 Sch=JB1_N
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#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L16P_T2_34 Sch=JB2_P
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#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L16N_T2_34 Sch=JB2_N
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#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L17P_T2_34 Sch=JB3_P
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#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L17N_T2_34 Sch=JB3_N
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#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L22P_T3_34 Sch=JB4_P
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#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L22N_T3_34 Sch=JB4_N
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##Pmod Header JC
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#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { jc_p[0] }]; #IO_L10P_T1_34 Sch=JC1_P
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#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { jc_n[0] }]; #IO_L10N_T1_34 Sch=JC1_N
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#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jc_p[1] }]; #IO_L1P_T0_34 Sch=JC2_P
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#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jc_n[1] }]; #IO_L1N_T0_34 Sch=JC2_N
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#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jc_p[2] }]; #IO_L8P_T1_34 Sch=JC3_P
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#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jc_n[2] }]; #IO_L8N_T1_34 Sch=JC3_N
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#set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { jc_p[3] }]; #IO_L2P_T0_34 Sch=JC4_P
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#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc_n[3] }]; #IO_L2N_T0_34 Sch=JC4_N
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##Pmod Header JD
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#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[0] }]; #IO_L5P_T0_34 Sch=JD1_P
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#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[0] }]; #IO_L5N_T0_34 Sch=JD1_N
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#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[1] }]; #IO_L6P_T0_34 Sch=JD2_P
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#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { jd_n[1] }]; #IO_L6N_T0_VREF_34 Sch=JD2_N
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#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jd_p[2] }]; #IO_L11P_T1_SRCC_34 Sch=JD3_P
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#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { jd_n[2] }]; #IO_L11N_T1_SRCC_34 Sch=JD3_N
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#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { jd_p[3] }]; #IO_L21P_T3_DQS_34 Sch=JD4_P
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#set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { jd_n[3] }]; #IO_L21N_T3_DQS_34 Sch=JD4_N
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##Pmod Header JE
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#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { je[0] }]; #IO_L4P_T0_34 Sch=JE1
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#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { je[1] }]; #IO_L18N_T2_34 Sch=JE2
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#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { je[2] }]; #IO_25_35 Sch=JE3
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#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { je[3] }]; #IO_L19P_T3_35 Sch=JE4
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#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { je[4] }]; #IO_L3N_T0_DQS_34 Sch=JE7
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#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { je[5] }]; #IO_L9N_T1_DQS_34 Sch=JE8
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#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { je[6] }]; #IO_L20P_T3_34 Sch=JE9
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#set_property -dict { PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 } [get_ports { je[7] }]; #IO_L7N_T1_34 Sch=JE10
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##USB-OTG overcurrent detect pin
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#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { otg_oc }]; #IO_L3P_T0_DQS_PUDC_B_34 Sch=OTG_OC
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#VGA Connector
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set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { io_r[0] }]; #IO_L7P_T1_AD2P_35 Sch=VGA_R1
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set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { io_r[1] }]; #IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
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set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { io_r[2] }]; #IO_L17P_T2_AD5P_35 Sch=VGA_R3
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set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { io_r[3] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R4
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set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { io_r[4] }]; #IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
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set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { io_g[0] }]; #IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
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set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { io_g[1] }]; #IO_L14P_T2_SRCC_34 Sch=VGA_G1
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set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { io_g[2] }]; #IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
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set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { io_g[3] }]; #IO_L10N_T1_AD11N_35 Sch=VGA_G3
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set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { io_g[4] }]; #IO_L17N_T2_AD5N_35 Sch=VGA_G4
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set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { io_g[5] }]; #IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
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set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { io_b[0] }]; #IO_L14N_T2_SRCC_34 Sch=VGA_B1
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set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { io_b[1] }]; #IO_L7N_T1_AD2N_35 Sch=VGA_B2
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set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { io_b[2] }]; #IO_L10P_T1_AD11P_35 Sch=VGA_B3
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { io_b[3] }]; #IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
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set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { io_b[4] }]; #IO_L18P_T2_AD13P_35 Sch=VGA_B5
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set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { io_hs }]; #IO_L13N_T2_MRCC_34 Sch=VGA_HS
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set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { io_vs }]; #IO_0_34 Sch=VGA_VS
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61
common/bitstream.vivado.tcl
Normal file
61
common/bitstream.vivado.tcl
Normal file
@@ -0,0 +1,61 @@
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# Input arguments
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set DEVICE [lindex $argv 0]
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set TOP [lindex $argv 1]
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set REP [lindex $argv 2]
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set TARGET [lindex $argv 3]
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set MEM_FILE [file normalize [lindex $argv 4]]
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source common/reportCriticalPaths.tcl
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#lecture de tous les sv générés
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set files [glob RTL/${REP}.${TOP}/*.sv]
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read_verilog -sv $files
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#ajout de clock à 10 MHz et 125 MHz
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read_verilog -sv src/main/resources/vsrc/clk_wiz.v
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read_verilog -sv src/main/resources/vsrc/dpram.v
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set_param general.maxThreads 4
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# Reading constraint file (.xdc file)
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read_xdc common/${TOP}.xdc
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# Detect XPM memory
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auto_detect_xpm
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# Start synthesis
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synth_design -top ${TOP} -part ${DEVICE} -fanout_limit 100
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#-flatten_hierarchy none
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#-directive RuntimeOptimized
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# Run logic optimization
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opt_design
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# Placing
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place_design
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#-directive Quick
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#write_checkpoint -force place_design.dcp
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# Routing
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route_design -ultrathreads
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# -directive Quick
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#write_checkpoint -force route_design.dcp
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# Reports
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report_timing -file ${TOP}_timing.rpt
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report_timing_summary -max_paths 500 -nworst 1 -input_pins -file ${TOP}_timing_summary.rpt
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report_utilization -file ${TOP}_utilization_opt.rpt
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report_critical_paths ${TOP}_critpath_report.csv
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report_route_status -file ${TOP}_route_status.rpt
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report_design_analysis -file ${TOP}_design_analysis.rpt
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report_io -file ${TOP}_io_opt.rpt
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report_drc -file ${TOP}_drc_route.rpt
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report_clock_interaction -file ${TOP}_clock_interaction_opt.rpt
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# Generate MMI map
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write_mem_info -force ${TOP}.mmi
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# Create bitstream
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write_bitstream -force ${TARGET}
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write_checkpoint -force bitstream_design.dcp
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exit
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5
common/clock.xdc
Normal file
5
common/clock.xdc
Normal file
@@ -0,0 +1,5 @@
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# Clock signal
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||||
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clock }];
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set_input_delay -clock sys_clk_pin 0.000 [all_inputs]
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set_output_delay -clock sys_clk_pin 0.000 [all_outputs]
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||||
76
common/config.gtkw
Normal file
76
common/config.gtkw
Normal file
@@ -0,0 +1,76 @@
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||||
[*]
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||||
[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
|
||||
[*] Mon Nov 3 08:12:34 2025
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||||
[*]
|
||||
[dumpfile] "/user/9/.base/mullero/home/cours/FMN/projet/build/chiselsim/ZzTopSpec/Simulation-pour-gtkwave/workdir-verilator/trace.vcd"
|
||||
[dumpfile_mtime] "Mon Nov 3 08:11:19 2025"
|
||||
[dumpfile_size] 59916
|
||||
[savefile] "/user/9/.base/mullero/home/cours/FMN/projet/common/config.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1920 1080
|
||||
[pos] -67 -33
|
||||
*-14.058537 52 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] TOP.
|
||||
[treeopen] TOP.svsimTestbench.
|
||||
[treeopen] TOP.svsimTestbench.dut.
|
||||
[treeopen] TOP.svsimTestbench.dut.core.
|
||||
[sst_width] 278
|
||||
[signals_width] 142
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 317
|
||||
@200
|
||||
-Instruction
|
||||
@c04023
|
||||
^>1 /matieres/3MMFMN/riscv32/bin/spike-dasm
|
||||
TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
@29
|
||||
(0)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(1)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(2)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(3)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(4)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(5)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(6)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(7)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(8)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(9)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(10)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(11)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(12)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(13)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(14)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(15)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(16)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(17)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(18)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(19)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(20)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(21)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(22)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(23)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(24)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(25)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(26)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(27)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(28)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(29)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(30)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
(31)TOP.svsimTestbench.dut.core.insn[31:0]
|
||||
@1401201
|
||||
-group_end
|
||||
@22
|
||||
TOP.svsimTestbench.dut.core.pc[31:0]
|
||||
TOP.svsimTestbench.dut.core.rd[4:0]
|
||||
TOP.svsimTestbench.dut.core.rs1Value[31:0]
|
||||
TOP.svsimTestbench.dut.core.rs2Value[31:0]
|
||||
TOP.svsimTestbench.dut.core.wbVal[31:0]
|
||||
@28
|
||||
TOP.svsimTestbench.dut.core.clock
|
||||
TOP.svsimTestbench.dut.core.reset
|
||||
@22
|
||||
TOP.svsimTestbench.dut.io_x31[31:0]
|
||||
@28
|
||||
TOP.svsimTestbench.dut.io_valid_x31
|
||||
TOP.svsimTestbench.dut.core.rdValid
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
27
common/fix_mem.awk
Normal file
27
common/fix_mem.awk
Normal file
@@ -0,0 +1,27 @@
|
||||
BEGIN {
|
||||
addr = 0
|
||||
first = 1
|
||||
}
|
||||
|
||||
# Ligne adresse : @xxxx
|
||||
/^@/ {
|
||||
newAddr = strtonum("0x" substr($0, 2))
|
||||
if (first) {
|
||||
print $0 # garde le premier @xxxx (normalement @0000)
|
||||
first = 0
|
||||
} else {
|
||||
while (addr < newAddr) {
|
||||
print "00000000"
|
||||
addr++
|
||||
}
|
||||
}
|
||||
next
|
||||
}
|
||||
|
||||
# Ligne(s) de données
|
||||
{
|
||||
for (i = 1; i <= NF; i++) {
|
||||
print $i
|
||||
addr++
|
||||
}
|
||||
}
|
||||
73
common/objtomem.awk
Executable file
73
common/objtomem.awk
Executable file
@@ -0,0 +1,73 @@
|
||||
# On utilise désormais objdump -s pour se faciliter la vie
|
||||
# Contenu de la section .text :
|
||||
# 1000 930f0000 930f7000 930fc0ff 93004000 ......p.......@.
|
||||
# 1010 938f0000 938f3000 938fd0ff 1301c0ff ......0.........
|
||||
# 1020 930f3100 930fd1ff 9301f07f 938f1100 ..1.............
|
||||
# 1030 13020080 930ff2ff 13030001 930f0301 ................
|
||||
# 1040 930300ff 938f03ff 37040080 1304f4ff ........7.......
|
||||
# 1050 930f1400 9304f0ff 938f1400 938f2403 ..............$.
|
||||
# 1060 eff05ffa .._.
|
||||
# Contenu de la section .data :
|
||||
# 1064 78563412 cacaefbe adde0000 00000000 xV4.............
|
||||
# 1074 00000000 0000 ......
|
||||
|
||||
function swapbytes(drow) {
|
||||
return substr(drow, 7, 2) substr(drow, 5, 2) substr(drow, 3, 2) substr(drow, 1, 2)
|
||||
}
|
||||
|
||||
function writemem(addr, section) {
|
||||
printf("@%08x\n", addr) # Adresse formatée
|
||||
# On a aligné sur un multiple de 8, let's go
|
||||
for (i = 1; i < length(section); i += 8) {
|
||||
print(substr(section, i, 8));
|
||||
}
|
||||
print "deadc0de" # Balise de fin de section (constante)
|
||||
}
|
||||
|
||||
# Ligne donnant l'info de la section
|
||||
# Toujours trouvée avant le reste
|
||||
/^Contenu|^Contents/ {
|
||||
if (content) {
|
||||
writemem(start_addr, content)
|
||||
}
|
||||
# En toute logique on pourrait mettre là le nom de section, mais
|
||||
# ça dépend de la locale, donc pour l'instant on laisse tomber
|
||||
section = 1
|
||||
content = ""
|
||||
}
|
||||
|
||||
/^\s*[0-9a-f]+/ {
|
||||
if (section) {
|
||||
addr = strtonum("0x" $1)
|
||||
start_addr = strtonum("0x" $1) / 4
|
||||
if (addr != start_addr * 4) {
|
||||
print("Début de section non alignée : "addr) > "/dev/stderr"
|
||||
exit
|
||||
}
|
||||
section = 0;
|
||||
}
|
||||
|
||||
for (i = 2; i <= NR; i++) {
|
||||
v = $i
|
||||
if (v ~ /[0-9a-f]{2,8}/) {
|
||||
# Le dernier nombre peut avoir une taille 2, 4, 6, 8
|
||||
if (length(v) == 6) {
|
||||
v = v "00"
|
||||
} else if (length($i) == 4) {
|
||||
v = v "0000"
|
||||
} else if (length($i) == 2) {
|
||||
v = v "000000"
|
||||
} else if (length($i) != 8) {
|
||||
# Pour la partie avec les '.'
|
||||
continue;
|
||||
}
|
||||
content = content swapbytes(v)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
END {
|
||||
if (content) {
|
||||
writemem(start_addr, content)
|
||||
}
|
||||
}
|
||||
98
common/parse_report.py
Normal file
98
common/parse_report.py
Normal file
@@ -0,0 +1,98 @@
|
||||
import sys
|
||||
import os
|
||||
|
||||
def extractPrimitives(fileName, destName):
|
||||
f = open(fileName, "r")
|
||||
print("Needed primitives:")
|
||||
print("------------------")
|
||||
br = False
|
||||
cnt = 0
|
||||
while (not br):
|
||||
line = f.readline()
|
||||
if 'Primitives' in line:
|
||||
br = (cnt == 1)
|
||||
cnt += 1
|
||||
f.readline()
|
||||
f.readline()
|
||||
line = f.readline()
|
||||
while (line != "\n"):
|
||||
print(line[:-1])
|
||||
line = f.readline()
|
||||
f.close()
|
||||
|
||||
def extractUtilization(fileName, destName):
|
||||
f = open(fileName, "r")
|
||||
print("Real utilization:")
|
||||
print("-----------------")
|
||||
for line in f.readlines():
|
||||
if 'Slice LUTs' in line:
|
||||
number = line.split("|")[2].strip()
|
||||
perc = line.split("|")[5].strip()
|
||||
print("LUT6s : {} ({}%)".format(number, perc))
|
||||
if 'Register as Flip Flop' in line:
|
||||
number = line.split("|")[2].strip()
|
||||
perc = line.split("|")[5].strip()
|
||||
print("Flops : {} ({}%)".format(number, perc))
|
||||
if ('Block RAM Tile' in line) and ('Note' not in line):
|
||||
number = line.split("|")[2].strip()
|
||||
perc = line.split("|")[5].strip()
|
||||
print("BRAMs : {} ({}%)".format(number, perc))
|
||||
if 'DSPs' in line:
|
||||
number = line.split("|")[2].strip()
|
||||
perc = line.split("|")[5].strip()
|
||||
print("DSPs : {} ({}%)".format(number, perc))
|
||||
f.close()
|
||||
print("")
|
||||
|
||||
def extractPathDelay(fileName):
|
||||
f = open(fileName, "r")
|
||||
for line in f.readlines():
|
||||
if 'Data Path Delay' in line:
|
||||
delay = float(line.split(":")[1].strip().split(" ")[0].strip().split("ns")[0].strip())
|
||||
f.close()
|
||||
return delay
|
||||
f.close()
|
||||
print("Did not found any Data Path in circuit")
|
||||
return float("NaN")
|
||||
|
||||
def extractClock(summaryFileName, timingFileName):
|
||||
f = open(summaryFileName, "r")
|
||||
clock = ''
|
||||
slack = ''
|
||||
for line in f.readlines():
|
||||
if 'Clock' in line:
|
||||
try:
|
||||
clock = float(line.split("|")[1].strip())
|
||||
except:
|
||||
# Clock line was found in report, but not with a numeric value associated
|
||||
# This is probably due to a circuit optimization where all sequential logic
|
||||
# has been evinced - e.g. output stick to a constant, ...
|
||||
pass
|
||||
if 'Slack' in line:
|
||||
try:
|
||||
slack = float(line.split("|")[1].strip())
|
||||
except:
|
||||
# Same
|
||||
pass
|
||||
f.close()
|
||||
print("Timing analysis:")
|
||||
print("----------------")
|
||||
if (clock == '' or slack == ''):
|
||||
clock = float("NaN")
|
||||
slack = float("NaN")
|
||||
path = extractPathDelay(timingFileName)
|
||||
else:
|
||||
path = (clock-slack)
|
||||
freq = (1.0/(path*pow(10, -9)))/pow(10,6)
|
||||
print("Clock : %4.2f ns" % clock)
|
||||
print("Slack : %4.2f ns" % slack)
|
||||
print("Path : %4.2f ns" % path)
|
||||
print("Freq : %4.2f MHz" % freq)
|
||||
|
||||
if __name__=="__main__":
|
||||
if (len(sys.argv) != 4):
|
||||
sys.exit("Usage python parse_report.py <utilizationReport> <timingReport> <destinationReport>")
|
||||
print("\n--------- Résumé ----------\n")
|
||||
extractClock(sys.argv[3], sys.argv[2])
|
||||
extractUtilization(sys.argv[1], sys.argv[3])
|
||||
extractPrimitives(sys.argv[1], sys.argv[3])
|
||||
24
common/programFPGA.vivado.tcl
Normal file
24
common/programFPGA.vivado.tcl
Normal file
@@ -0,0 +1,24 @@
|
||||
# Inputs arguments
|
||||
set BIT_FILE [lindex $argv 0]
|
||||
|
||||
# Open hardware mode
|
||||
open_hw
|
||||
|
||||
# Connect target
|
||||
connect_hw_server
|
||||
refresh_hw_server
|
||||
set targets [get_hw_targets]
|
||||
puts "targets: ${targets}"
|
||||
current_hw_target [lindex ${targets} 0]
|
||||
open_hw_target
|
||||
|
||||
# Select device
|
||||
set devices [get_hw_devices]
|
||||
puts "devices: ${devices}"
|
||||
|
||||
# Program
|
||||
set_property PROGRAM.FILE ${BIT_FILE} [lindex [get_hw_devices] 1]
|
||||
|
||||
program_hw_devices
|
||||
refresh_hw_device
|
||||
|
||||
4
common/programFPGA.xsdb.tcl
Normal file
4
common/programFPGA.xsdb.tcl
Normal file
@@ -0,0 +1,4 @@
|
||||
connect
|
||||
target 4
|
||||
fpga download.bit
|
||||
exit
|
||||
28
common/reportCriticalPaths.tcl
Normal file
28
common/reportCriticalPaths.tcl
Normal file
@@ -0,0 +1,28 @@
|
||||
proc report_critical_paths { filename } {
|
||||
|
||||
# Open the specified output file in write mode
|
||||
set FH [open $filename w]
|
||||
# Write the current date and CSV format to a file header
|
||||
puts $FH "#\n# File created on [clock format [clock seconds]]\n#\n"
|
||||
puts $FH "Startpoint,Endpoint,Slack,#Levels,#LUTs"
|
||||
# Collect details from the 50 worst timing paths for the current analysis
|
||||
# The $path variable contains a Timing Path object.
|
||||
foreach path [get_timing_paths -max_paths 500 -nworst 1] {
|
||||
# Get the LUT cells of the timing paths
|
||||
set luts [get_cells -filter {REF_NAME =~ LUT*} -of_object $path]
|
||||
# Get the startpoint of the Timing Path object
|
||||
set startpoint [get_property STARTPOINT_PIN $path]
|
||||
# Get the endpoint of the Timing Path object
|
||||
set endpoint [get_property ENDPOINT_PIN $path]
|
||||
# Get the slack on the Timing Path object
|
||||
set slack [get_property SLACK $path]
|
||||
# Get the number of logic levels between startpoint and endpoint
|
||||
set levels [get_property LOGIC_LEVELS $path]
|
||||
# Save the collected path details to the CSV file
|
||||
puts $FH "$startpoint,$endpoint,$slack,$levels,[llength $luts]"
|
||||
}
|
||||
# Close the output file
|
||||
close $FH
|
||||
puts "CSV file $filename has been created.\n"
|
||||
return 0
|
||||
}; # End PROC
|
||||
35
common/synthese.vivado.tcl
Normal file
35
common/synthese.vivado.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# Input arguments
|
||||
set DEVICE [lindex $argv 0]
|
||||
set TOP [lindex $argv 1]
|
||||
set REP [lindex $argv 2]
|
||||
|
||||
#lecture de tous les sv générés
|
||||
set files [glob RTL/${REP}.${TOP}/*.sv]
|
||||
read_verilog -sv $files
|
||||
read_verilog -sv src/main/resources/vsrc/clk_wiz.v
|
||||
read_verilog -sv src/main/resources/vsrc/dpram.v
|
||||
|
||||
read_xdc common/clock.xdc
|
||||
# Detect XPM memory
|
||||
auto_detect_xpm
|
||||
|
||||
# Start synthesis
|
||||
synth_design -top ${TOP} -part ${DEVICE} -mode "out_of_context"
|
||||
report_utilization -file ${TOP}_utilization.rpt
|
||||
report_timing -file ${TOP}_timing.rpt
|
||||
report_clocks
|
||||
|
||||
get_ports *
|
||||
|
||||
set filename "${TOP}_summary.rpt"
|
||||
set fileId [open $filename "w"]
|
||||
if { [get_clocks] != "" } {
|
||||
puts -nonewline $fileId "Clock | "
|
||||
puts $fileId [get_property -min PERIOD [get_clocks]];
|
||||
}
|
||||
if { [get_timing_paths] != "" } {
|
||||
puts -nonewline $fileId "Slack | "
|
||||
puts $fileId [get_property SLACK [get_timing_paths]];
|
||||
}
|
||||
close $fileId
|
||||
exit
|
||||
Reference in New Issue
Block a user