62 lines
1.6 KiB
Tcl
62 lines
1.6 KiB
Tcl
# Input arguments
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set DEVICE [lindex $argv 0]
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set TOP [lindex $argv 1]
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set REP [lindex $argv 2]
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set TARGET [lindex $argv 3]
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set MEM_FILE [file normalize [lindex $argv 4]]
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source common/reportCriticalPaths.tcl
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#lecture de tous les sv générés
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set files [glob RTL/${REP}.${TOP}/*.sv]
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read_verilog -sv $files
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#ajout de clock à 10 MHz et 125 MHz
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read_verilog -sv src/main/resources/vsrc/clk_wiz.v
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read_verilog -sv src/main/resources/vsrc/dpram.v
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set_param general.maxThreads 4
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# Reading constraint file (.xdc file)
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read_xdc common/${TOP}.xdc
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# Detect XPM memory
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auto_detect_xpm
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# Start synthesis
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synth_design -top ${TOP} -part ${DEVICE} -fanout_limit 100
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#-flatten_hierarchy none
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#-directive RuntimeOptimized
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# Run logic optimization
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opt_design
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# Placing
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place_design
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#-directive Quick
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#write_checkpoint -force place_design.dcp
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# Routing
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route_design -ultrathreads
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# -directive Quick
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#write_checkpoint -force route_design.dcp
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# Reports
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report_timing -file ${TOP}_timing.rpt
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report_timing_summary -max_paths 500 -nworst 1 -input_pins -file ${TOP}_timing_summary.rpt
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report_utilization -file ${TOP}_utilization_opt.rpt
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report_critical_paths ${TOP}_critpath_report.csv
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report_route_status -file ${TOP}_route_status.rpt
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report_design_analysis -file ${TOP}_design_analysis.rpt
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report_io -file ${TOP}_io_opt.rpt
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report_drc -file ${TOP}_drc_route.rpt
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report_clock_interaction -file ${TOP}_clock_interaction_opt.rpt
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# Generate MMI map
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write_mem_info -force ${TOP}.mmi
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# Create bitstream
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write_bitstream -force ${TARGET}
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write_checkpoint -force bitstream_design.dcp
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exit
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