43 lines
1.6 KiB
Markdown
43 lines
1.6 KiB
Markdown
This repository contains a podman image whichs includes all the necessary tools to generate and flash a bitstream file from a SystemVerilog program.
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It is built for the Xilinx Zybo Zynq7 `xc7z010` card, but it can probably be easily adapted to support another board.
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# Installation
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You will need [podman](https://podman.io/) to run the image.
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## Use the pre-built image
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You can directly use the pre-built image available in the repository :
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```bash
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zstd -d fmn.tar.zst
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podman load --input fmn.tar
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```
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## Build the image from source
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You can build the image yourself by using this command :
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```bash
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podman build -t fmn_alpine .
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```
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It will first create an image that builds all the tools, and then generate the final image containing only the necessary binaries and libraries.
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For reference, it takes about 5.63GB of space and 10 minutes to build on my machine.
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# Tools
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- [sv2v](https://github.com/zachjs/sv2v) : Converts SystemVerilog to Verilog.
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- [yosys](https://github.com/YosysHQ/yosys) : Performs RTL synthesis from verilog files.
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- [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) : placing and routing tool.
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- [fasm2frames](https://github.com/f4pga/prjxray) : Converts fasm files to frames files.
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- [xc7frames2bit](https://github.com/f4pga/prjxray) : Converts frames files to bitstream.
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- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flashes a bitstream onto an FPGA card.
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The image also includes some [databases](https://github.com/f4pga/prjxray-db) required for the prjxray tools to function.
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# Usage
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See the provided [example](./example/).
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