This repository contains a podman image whichs includes all the necessary tools to generate and flash a bitstream file from a SystemVerilog program.
It is built for the Xilinx Zybo Zynq7 `xc7z010` card, but it can probably be easily adapted to support another board.

# Installation

You will need [podman](https://podman.io/) to run the image.

## Use the pre-built image

You can directly use the pre-built image available in the repository :

```bash
zstd -d fmn.tar.zst
podman load --input fmn.tar
```

## Build the image from source

You can build the image yourself by using this command :

```bash
podman build -t fmn_alpine .
```

It will first create an image that builds all the tools, and then generate the final image containing only the necessary binaries and libraries.

For reference, it takes about 5.63GB of space and 10 minutes to build on my machine.

# Tools

- [sv2v](https://github.com/zachjs/sv2v) : Converts SystemVerilog to Verilog.
- [yosys](https://github.com/YosysHQ/yosys) : Performs RTL synthesis from verilog files.
- [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) : placing and routing tool.
- [fasm2frames](https://github.com/f4pga/prjxray) : Converts fasm files to frames files.
- [xc7frames2bit](https://github.com/f4pga/prjxray) : Converts frames files to bitstream.
- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flashes a bitstream onto an FPGA card.

The image also includes some [databases](https://github.com/f4pga/prjxray-db) required for the prjxray tools to function.

# Usage

See the provided [example](./example/).