Add podman image and README
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14
example/adder.sv
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14
example/adder.sv
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module AC(
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input clock,
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io_a,
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io_b,
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io_c,
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output io_s,
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io_co
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);
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wire tmp = io_a ^ io_b;
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assign io_s = tmp ^ io_c;
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assign io_co = io_a & io_b | tmp & io_c;
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endmodule
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