diff --git a/README.md b/README.md
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+This repository contains a podman image whichs contains all necessary tools to generate and flash bitstream file from a SystemVerilog program.
+It is build for the xilinx zybo zynq7 `xc7z010` card, but it can probably be easily edited to support another card.
+
+# Installation
+
+You will need [podman](https://podman.io/) to run the image.
+
+## Use the pre-built image
+
+You can directly use the pre-build image present in the repo
+
+```bash
+zstd -d fmn.tar.zst
+podman load --input fmn.tar
+```
+
+## Build the image from source
+
+You can build the image yourself by using this command:
+
+```bash
+podman build -t fmn_alpine .
+```
+
+It will first create an image which will build every tools, and then create the final image containing only needed binaries and libraries.
+
+For information, it takes around 5.63GB space and 10 minutes to build on my device.
+
+# Tools
+
+- [sv2v](https://github.com/zachjs/sv2v) : Convert SystemVerilog to Verilog.
+- [yosys](https://github.com/YosysHQ/yosys) : Do RTL synthesis from verilog files.
+- [nextpnr-himbaechel](https://github.com/YosysHQ/nextpnr) : placing and routing tool.
+- [fasm2frames](https://github.com/f4pga/prjxray) : Convert fasm files to frames files.
+- [xc7frames2bit](https://github.com/f4pga/prjxray) : Convert frames files to bitstream.
+- [openFPGALoader](https://github.com/trabucayre/openFPGALoader) : Flash a bitstream on a FPGA card.
+
+The image also contains some [databases](https://github.com/f4pga/prjxray-db) needed for prjxray tools to work.
+
+# Usage
+
+See the small [example](./example/).
diff --git a/example/.gitignore b/example/.gitignore
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+abc.history
+adder.v
+out.bin
+out.fasm
+out.frames
+synthesis.json
diff --git a/example/README.md b/example/README.md
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+# Example
+
+This directory shows how to flash a system verilog program (A full-adder) on a Zybo `xc7z010clg400-1` card.
+
+## Build
+
+Firstly, the system verilog file needs to be converted to verilog in order to use it with yosys :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine sv2v adder.sv -w adder.v
+```
+
+The mount parameter is used to provide to podman the current directory.
+
+Then, yosys can achieve the RTL synthesis of the program :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine yosys adder.v -p "synth_xilinx; write_json synthesis.json"
+```
+
+Nextpnr can now place and route each components using the xdc constraints file :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine nextpnr-himbaechel --json synthesis.json -o xdc=adder.xdc -o fasm=out.fasm --device xc7z010clg400-1
+```
+
+Now the fasm file can be converted in a frames file and then in a bitstream :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine fasm2frames --part xc7z010clg400-1 --db-root /usr/share/xray/database/zynq7 out.fasm out.frames
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine xc7frames2bit -frm_file out.frames -part_file /usr/share/xray/database/zynq7/xc7z010clg400-1/part.yaml --output_file out.bin
+```
+
+## Flashing the FPGA
+
+Finally, we can flash the bitstream on the card with `openFPGALoader`.
+
+Podman requires a device argument to allow openFPGALoader to access the usb interface. You can find this path with `lsusb` :
+
+```txt
+Bus 003 Device 005: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
+```
+
+Here the usb device path is `/dev/bus/usb/003/005`
+
+```bash
+podman run --device=/dev/bus/usb/003/005 --mount=type=bind,source=.,target=/root/code fmn_alpine openFPGALoader -b zybo_z7_10 out.bin
+```
diff --git a/example/adder.sv b/example/adder.sv
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+module AC(
+  input  clock,
+         io_a,
+         io_b,
+         io_c,
+  output io_s,
+         io_co
+);
+
+  wire tmp = io_a ^ io_b;
+  assign io_s = tmp ^ io_c;
+  assign io_co = io_a & io_b | tmp & io_c;
+endmodule
+
diff --git a/example/adder.xdc b/example/adder.xdc
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+# Create a clock
+set_property PACKAGE_PIN L16     [get_ports clock]
+set_property IOSTANDARD LVCMOS33 [get_ports clock]
+
+create_clock -period 8.00 [get_ports  clock]
+
+# Buttons
+set_property PACKAGE_PIN G15     [get_ports io_a]
+set_property IOSTANDARD LVCMOS33 [get_ports io_a]
+set_property PACKAGE_PIN P15     [get_ports io_b]
+set_property IOSTANDARD LVCMOS33 [get_ports io_b]
+set_property PACKAGE_PIN W13     [get_ports io_c]
+set_property IOSTANDARD LVCMOS33 [get_ports io_c]
+
+# LEDs
+set_property PACKAGE_PIN M14     [get_ports io_s]
+set_property IOSTANDARD LVCMOS33 [get_ports io_s]
+set_property PACKAGE_PIN M15     [get_ports io_co]
+set_property IOSTANDARD LVCMOS33 [get_ports io_co]
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