Add podman image and README

example/.gitignore

@@ -0,0 +1,6 @@
+abc.history
+adder.v
+out.bin
+out.fasm
+out.frames
+synthesis.json

example/README.md

@@ -0,0 +1,48 @@
+# Example
+
+This directory shows how to flash a system verilog program (A full-adder) on a Zybo `xc7z010clg400-1` card.
+
+## Build
+
+Firstly, the system verilog file needs to be converted to verilog in order to use it with yosys :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine sv2v adder.sv -w adder.v
+```
+
+The mount parameter is used to provide to podman the current directory.
+
+Then, yosys can achieve the RTL synthesis of the program :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine yosys adder.v -p "synth_xilinx; write_json synthesis.json"
+```
+
+Nextpnr can now place and route each components using the xdc constraints file :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine nextpnr-himbaechel --json synthesis.json -o xdc=adder.xdc -o fasm=out.fasm --device xc7z010clg400-1
+```
+
+Now the fasm file can be converted in a frames file and then in a bitstream :
+
+```bash
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine fasm2frames --part xc7z010clg400-1 --db-root /usr/share/xray/database/zynq7 out.fasm out.frames
+podman run --mount=type=bind,source=.,target=/root/code fmn_alpine xc7frames2bit -frm_file out.frames -part_file /usr/share/xray/database/zynq7/xc7z010clg400-1/part.yaml --output_file out.bin
+```
+
+## Flashing the FPGA
+
+Finally, we can flash the bitstream on the card with `openFPGALoader`.
+
+Podman requires a device argument to allow openFPGALoader to access the usb interface. You can find this path with `lsusb` :
+
+```txt
+Bus 003 Device 005: ID 0403:6010 Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
+```
+
+Here the usb device path is `/dev/bus/usb/003/005`
+
+```bash
+podman run --device=/dev/bus/usb/003/005 --mount=type=bind,source=.,target=/root/code fmn_alpine openFPGALoader -b zybo_z7_10 out.bin
+```

example/adder.sv

@@ -0,0 +1,14 @@
+module AC(
+  input  clock,
+         io_a,
+         io_b,
+         io_c,
+  output io_s,
+         io_co
+);
+
+  wire tmp = io_a ^ io_b;
+  assign io_s = tmp ^ io_c;
+  assign io_co = io_a & io_b | tmp & io_c;
+endmodule
+

example/adder.xdc

@@ -0,0 +1,19 @@
+# Create a clock
+set_property PACKAGE_PIN L16     [get_ports clock]
+set_property IOSTANDARD LVCMOS33 [get_ports clock]
+
+create_clock -period 8.00 [get_ports  clock]
+
+# Buttons
+set_property PACKAGE_PIN G15     [get_ports io_a]
+set_property IOSTANDARD LVCMOS33 [get_ports io_a]
+set_property PACKAGE_PIN P15     [get_ports io_b]
+set_property IOSTANDARD LVCMOS33 [get_ports io_b]
+set_property PACKAGE_PIN W13     [get_ports io_c]
+set_property IOSTANDARD LVCMOS33 [get_ports io_c]
+
+# LEDs
+set_property PACKAGE_PIN M14     [get_ports io_s]
+set_property IOSTANDARD LVCMOS33 [get_ports io_s]
+set_property PACKAGE_PIN M15     [get_ports io_co]
+set_property IOSTANDARD LVCMOS33 [get_ports io_co]