Add more from the std

.cargo/config.toml

@@ -3,10 +3,9 @@ target = "riscv64.json"
 
 [unstable]
 json-target-spec = true
-# build-std = []
-# build-std-features = ["compiler-builtins-mem"]
 
 [target.riscv64]
 rustflags = [
   "-C", "link-arg=-Tilm.ld",
+  "--sysroot", "sysroot"
 ]

crates/kernel-macros/Cargo.toml

@@ -7,6 +7,6 @@ edition = "2024"
 proc-macro = true
 
 [dependencies]
-image = "0.25"
+image = { version = "0.25", default-features = false, features = ["png"] }
 syn = { version = "2", features = ["full"] }
 zyn = "0.5"

justfile

@@ -1,7 +1,6 @@
 release := ""
 qemu_flags := ""
 cargo_flags := "" + if release != "" { "--release" } else { "" }
-KERNEL_FLAGS := "-Zbuild-std=core,compiler_builtins,alloc -Zbuild-std-features=compiler-builtins-mem"
 bin_path := if release != "" { "target/riscv64/release" } else { "target/riscv64/debug" }
 
 default: run
@@ -20,12 +19,12 @@ build-sysroot:
     @cd library/std && just build-sysroot
 
 build_user_prog prog:
-    RUSTFLAGS="-C relocation-model=pic -C link-arg=-Tuser.ld -C link-arg=-pie --sysroot {{ justfile_directory() / "sysroot" }}" cargo b {{ cargo_flags }} --package {{ prog }}
+    RUSTFLAGS="-C relocation-model=pic -C link-arg=-pie --sysroot {{ justfile_directory() / "sysroot" }}" cargo b {{ cargo_flags }} --package {{ prog }}
     riscv64-elf-strip {{ bin_path / prog }}
     cp {{ bin_path / prog }} {{ "mnt/usr/bin" / prog }}
 
 build: mount_filesystem (map_dir "user" f"just release=\"{{release}}\" cargo_flags=\"{{cargo_flags}}\" build_user_prog")
-    cargo b {{ cargo_flags }} {{ KERNEL_FLAGS }}
+    RUSTFLAGS="-Clink-arg=-Tilm.ld --sysroot {{ justfile_directory() / "sysroot" }}" cargo b {{ cargo_flags }}
     just sync_filesystem
 
 run: build (runner f"{{bin_path / "kernel-rust"}}")

library/.gitignore

@@ -12,5 +12,6 @@ rustc-std-workspace-alloc
 rustc-std-workspace-core
 rustc-std-workspace-std
 windows_link
+profiler_builtins
 test
 proc_macro

library/std/.gitignore

@@ -1,3 +1,5 @@
+build.rs
+
 src/alloc.rs
 src/ascii.rs
 src/backtrace.rs

user.ld

@@ -1,35 +0,0 @@
-/*
- * ld directives the for barmetal RISCV
- */
-OUTPUT_ARCH(riscv)
-ENTRY(_start)
-
-MEMORY {
-    RAM (wxa) : ORIGIN = 0x0, LENGTH = 128M
-}
-
-SECTIONS {
-    . = 0x0;
-    .text : {
-        KEEP(*(.text._start))
-
-        *(.text .text.*)
-    } > RAM
-
-    .rodata : {
-        *(.rodata .rodata.*)
-    }  > RAM
-
-    .data : {
-        *(.data .data.*)
-    }  > RAM
-
-    .bss : ALIGN(8) {
-        __bss_start = .;
-        *(.bss .bss.*)
-        __bss_end = .;
-    } > RAM
-
-    _heap_start = ALIGN(8);
-    _heap_end = ORIGIN(RAM) + LENGTH(RAM);
-}