Albin Chaboissier e35f2a4242 Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

2025-11-15 00:57:59 +01:00

..

op

Fixs merge conflict with word mode

2025-11-13 10:35:17 +01:00

Alu.scala

Rust character drawing

2025-11-14 09:57:42 +01:00

BusInterconnect.scala

Adds a way to simulate the programs with spike, to compare PCs and debug

2025-11-15 00:57:30 +01:00

CLint.scala

Formats code

2025-11-04 18:08:45 +01:00

ClockGen.scala

Formats code

2025-11-04 18:08:45 +01:00

Compteur.scala

Formats code

2025-11-04 18:08:45 +01:00

ControlUnit.scala

Fixs merge conflict with word mode

2025-11-13 10:35:17 +01:00

Delay.scala

Implements stage 3

2025-11-05 17:23:33 +01:00

DMem.scala

Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

2025-11-15 00:57:59 +01:00

GeneSync.scala

Formats code

2025-11-04 18:08:45 +01:00

IDMem.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00

ImmediateDecoder.scala

Corrects critical mistake in JAL, corrects VgaIp

2025-11-13 16:53:04 +01:00

LedIp.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00

RegFile.scala

Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

2025-11-15 00:57:59 +01:00

Rv64i.scala

Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

2025-11-15 00:57:59 +01:00

SignExtend.scala

Adds addiw instruction, all tests passing

2025-11-10 22:07:15 +01:00

VgaIp.scala

Corrects critical mistake in JAL, corrects VgaIp

2025-11-13 16:53:04 +01:00

ZzTop.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00