supersurviveur 7a1221b16e Merge branch 'rv64i' into rv64im

2025-11-11 19:17:46 +01:00

..

Alu.scala

Merge branch 'rv64i' into rv64im

2025-11-11 19:17:46 +01:00

BusInterconnect.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00

CLint.scala

Formats code

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ClockGen.scala

Formats code

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Compteur.scala

Formats code

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ControlUnit.scala

Merge branch 'rv64i' into rv64im

2025-11-11 19:17:46 +01:00

Delay.scala

Implements stage 3

2025-11-05 17:23:33 +01:00

DMem.scala

Lays groundword for Rv64i extension

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GeneSync.scala

Formats code

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IDMem.scala

Lays groundword for Rv64i extension

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ImmediateDecoder.scala

Lays groundword for Rv64i extension

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LedIp.scala

Lays groundword for Rv64i extension

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RegFile.scala

Lays groundword for Rv64i extension

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Rv64i.scala

Adds addiw instruction, all tests passing

2025-11-10 22:07:15 +01:00

SignExtend.scala

Adds addiw instruction, all tests passing

2025-11-10 22:07:15 +01:00

VgaIp.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00

ZzTop.scala

Lays groundword for Rv64i extension

2025-11-10 16:38:40 +01:00