Files
fmn_processor/bench/tests/op/lbu.s

13 lines
294 B
ArmAsm

# expected: 000000FB, 000000FB
.text
_start:
addi x1, x0, 0x0FB
nop # Next instruction depends on previous register op
sb x1, 100(x0)
lbu x31, 100(x0)
addi x1, x0, 0x0FB
nop # Next instruction depends on previous register op
sb x1, 106(x0)
lbu x31, 106(x0)