81 lines
2.0 KiB
Scala
81 lines
2.0 KiB
Scala
package projet
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import chisel3._
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class Rv32i(sim: Boolean = true) extends Module {
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val io = IO(new Bundle {
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val ibus = Flipped(new BusInterface)
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val dbus = Flipped(new BusInterface)
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val x31 = Output(UInt(32.W))
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val valid_x31 = if (sim) Some(Output(Bool())) else None
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})
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val reg_pc = RegInit(0.U(32.W));
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val reg_file = Module(new RegFile(sim));
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val instruction = io.ibus.rdata;
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reg_file.io.rd_data := 0.U;
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io.x31 := reg_file.io.x31
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if (sim) {
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io.valid_x31.get := reg_file.io.valid_x31.get && Delay.Delay(
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!reset.asBool,
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1,
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false.B
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)
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}
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val alu = Module(new Alu());
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val immediate_decoder = Module(new ImmediateDecoder());
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val control_unit = Module(new ControlUnit());
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immediate_decoder.io.instruction := instruction
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immediate_decoder.io.op_type := control_unit.io.optype
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alu.io.opcode := control_unit.io.alu_opcode;
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reg_file.io.we := control_unit.io.reg_file_we
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// Increment PC each clock
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reg_pc := reg_pc + 4.U;
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// PC delayed to execute stage for auipc op
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val execute_pc = Delay.Delay(reg_pc, 1, 0.U);
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// Fetch instruction
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io.ibus.en := true.B;
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io.ibus.addr := reg_pc;
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control_unit.io.instruction := instruction;
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// Decode rs1 index
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val rs1 = instruction(19, 15)
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reg_file.io.rs1_addr := rs1
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// Decode rs2 index
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val rs2 = instruction(24, 20)
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reg_file.io.rs2_addr := rs2
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// Decode rd index
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val rd = instruction(11, 7)
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reg_file.io.rd_addr := rd
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// EXECUTE
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val imm = immediate_decoder.io.immediate
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alu.io.a := Mux(
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control_unit.io.mux_rega_pc,
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reg_file.io.rs1_data,
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execute_pc
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);
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alu.io.b := imm;
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reg_file.io.rd_data := Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);
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io.dbus.addr := 0.U;
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io.dbus.wdata := 0.U;
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io.dbus.be := VecInit(false.B, false.B, false.B, false.B)
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io.dbus.en := false.B;
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io.ibus.wdata := 0.U;
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io.ibus.be := VecInit(false.B, false.B, false.B, false.B)
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// locally(sim)
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}
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