package projet

import chisel3._

class Rv32i(sim: Boolean = true) extends Module {
    val io = IO(new Bundle {
        val ibus = Flipped(new BusInterface)
        val dbus = Flipped(new BusInterface)
        val x31 = Output(UInt(32.W))
        val valid_x31 = if (sim) Some(Output(Bool())) else None
    })

    val reg_pc = RegInit(0.U(32.W));
    val reg_file = Module(new RegFile(sim));
    val instruction = io.ibus.rdata;

    reg_file.io.rd_data := 0.U;
    io.x31 := reg_file.io.x31
    if (sim) {
        io.valid_x31.get := reg_file.io.valid_x31.get && Delay.Delay(
            !reset.asBool,
            1,
            false.B
        )
    }

    val alu = Module(new Alu());
    val immediate_decoder = Module(new ImmediateDecoder());
    val control_unit = Module(new ControlUnit());

    immediate_decoder.io.instruction := instruction
    immediate_decoder.io.op_type := control_unit.io.optype
    alu.io.opcode := control_unit.io.alu_opcode;
    reg_file.io.we := control_unit.io.reg_file_we

    // Increment PC each clock
    reg_pc := reg_pc + 4.U;

    // PC delayed to execute stage for auipc op
    val execute_pc = Delay.Delay(reg_pc, 1, 0.U);

    // Fetch instruction
    io.ibus.en := true.B;
    io.ibus.addr := reg_pc;

    control_unit.io.instruction := instruction;

    // Decode rs1 index
    val rs1 = instruction(19, 15)
    reg_file.io.rs1_addr := rs1
    // Decode rs2 index
    val rs2 = instruction(24, 20)
    reg_file.io.rs2_addr := rs2
    // Decode rd index
    val rd = instruction(11, 7)
    reg_file.io.rd_addr := rd

    // EXECUTE

    val imm = immediate_decoder.io.immediate

    alu.io.a := Mux(
        control_unit.io.mux_rega_pc,
        reg_file.io.rs1_data,
        execute_pc
    );
    alu.io.b := imm;

    reg_file.io.rd_data := Mux(control_unit.io.mux_alu_imm, alu.io.out, imm);

    io.dbus.addr := 0.U;
    io.dbus.wdata := 0.U;
    io.dbus.be := VecInit(false.B, false.B, false.B, false.B)
    io.dbus.en := false.B;

    io.ibus.wdata := 0.U;
    io.ibus.be := VecInit(false.B, false.B, false.B, false.B)

    // locally(sim)
}