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Author SHA1 Message Date
surv 60d57b69bf Stage 10: test not passing 2025-11-08 18:56:19 +01:00
surv 43a11c865b Stage 10: not tested 2025-11-07 18:37:58 +01:00
octagonal 036f432d76 Stage 9: Full implemntation + passing tests 2025-11-07 18:03:45 +01:00
octagonal 2117f8155e Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-07 17:04:37 +01:00
octagonal a897778605 Modifies alu for branching instructions 2025-11-07 17:04:05 +01:00
surv 6dd2cf0298 Refactor Spec files 2025-11-07 15:54:04 +01:00
octagonal ea211d8a74 Reduces CPU cycles to 2 clock cycles for faster testing/simulation 2025-11-07 15:34:08 +01:00
octagonal e83e7c11c1 Stage 8: all tests passing 2025-11-07 15:27:15 +01:00
octagonal c88662403e Attempts to implement jalr, test not passing 2025-11-07 13:37:46 +01:00
octagonal 3828850dd6 Use nproc for parallel testing 2025-11-07 12:11:29 +01:00
octagonal 3761077b84 Merges build.sc 2025-11-07 12:03:27 +01:00
octagonal 479526a0fb Adds parallel testing 2025-11-07 12:02:17 +01:00
surv 99c5e0c78c Changes binary notation in ControlUnit to make formatter happy 2025-11-07 11:53:09 +01:00
surv 9c5313522d Merge branch 'main' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa 2025-11-07 11:51:43 +01:00
surv cbf7ec9ad3 Add jal instruction 2025-11-07 11:51:33 +01:00
octagonal 0e991583b9 Changes binary notation in ControlUnit to make formatter happy 2025-11-07 10:41:09 +01:00
octagonal 1adf33810f Add .csv to .gitignore 2025-11-07 10:38:39 +01:00
octagonal 47d290c5c2 Adds more vivado logs to .gitignore 2025-11-07 10:37:44 +01:00
octagonal a9790209fa Adds .rpt from gitignore to remove vivado logs 2025-11-07 10:35:57 +01:00
octagonal c2c16d9672 Stage 7: Register to register operations, all tests passing 2025-11-06 19:02:42 +01:00
surv 37435c6677 Add tests for stage 7 2025-11-06 18:52:31 +01:00
octagonal 1c829366de Implements stage 6: tests passing 2025-11-06 18:38:32 +01:00
surv 2ee9cc66b9 Refactor tests 2025-11-06 17:23:09 +01:00
surv a42235b6fd Refactor tests 2025-11-06 17:09:30 +01:00
surv 5f696dc8e7 Refactor tests 2025-11-06 16:34:17 +01:00
octagonal 2779471523 Stage 6: implementation, untested 2025-11-06 16:18:01 +01:00
surv 1462563e39 Implements stage 5 2025-11-05 20:01:41 +01:00
octagonal 5df85799ef Stage 4: Implements auipc 2025-11-05 18:40:27 +01:00
surv 3870e05613 Implements stage 3 2025-11-05 17:23:33 +01:00
surv 41c5da1a64 Formats code 2025-11-04 18:08:45 +01:00
surv fa60ce372f Implements stage 2 2025-11-04 18:06:00 +01:00
surv 2024c74bb4 Add spike-dasm 2025-11-04 15:59:40 +01:00
octagonal 7956338fbc Stage 1 + removes hardcoded paths 2025-11-04 15:41:33 +01:00
octagonal 5fa7f8949f Merge branch 'main' of gitlab.ensimag.fr:archi/FMN_projet 2025-11-04 14:47:13 +01:00
Olivier Muller cb3dddc77a ajout stage1 2025-11-04 14:29:47 +01:00
surv 79dbbc8f2a Update gitignore 2025-11-04 14:28:17 +01:00
surv f57d4d0bc4 Remove .bloop 2025-11-04 14:27:49 +01:00
surv 8ba14bcf42 Add .bloop to make chisel lsp and formatter happy 2025-11-04 14:08:41 +01:00
surv 2c77ed3bef Update makefile to get more logs and flash using openFPGALoader 2025-11-04 13:36:20 +01:00
Olivier Muller ff440776bb Squelette du projet 2025-11-03 11:00:11 +01:00