Implements stage 2

src/main/scala/projet/RegFile.scala

@@ -0,0 +1,29 @@
+package projet
+
+import chisel3._
+
+class RegFile(sim: Boolean = false) extends Module {
+    val io = IO(new Bundle {
+        val rs1_addr = Input(UInt(5.W))
+        val rs2_addr = Input(UInt(5.W))
+        val rd_addr = Input(UInt(5.W))
+        val rd_data = Input(UInt(32.W))
+        val we = Input(Bool())
+        val rs1_data = Output(UInt(32.W))
+        val rs2_data = Output(UInt(32.W))
+    })
+
+    val regs = Mem(32, UInt(32.W))
+
+    if (sim) {
+        when(reset.asBool) {
+            regs(0.U) := 0.U
+        }
+    }
+
+    when(io.we && io.rd_addr =/= 0.U) {
+        regs(io.rd_addr) := io.rd_data
+    }
+    io.rs1_data := regs(io.rs1_addr)
+    io.rs2_data := regs(io.rs2_addr)
+}

src/main/scala/projet/Rv32i.scala

@@ -11,27 +11,39 @@ class Rv32i(sim: Boolean = true) extends Module {
   })
 
   val reg_pc = RegInit(0.U(32.W));
+  val reg_file = Module(new RegFile(sim));
+  reg_file.io.rd_data := 0.U;
+  reg_file.io.we := 0.U;
 
   // Increment PC each clock
   reg_pc := reg_pc + 4.U;
 
-  // Read instruction
+  // Fetch instruction
   io.ibus.en := true.B;
   io.ibus.addr := reg_pc;
 
   val insn = io.ibus.rdata;
-  dontTouch(insn);
+
+  // Decode rs1 index
+  val rs1 = insn(19, 15)
+  reg_file.io.rs1_addr := rs1
+  // Decode rs2 index
+  val rs2 = insn(24, 20)
+  reg_file.io.rs2_addr := rs2
+  // Decode rd index
+  val rd = insn(11, 7)
+  reg_file.io.rd_addr := rd
+
+  // Decode imm-u
+  val imm_u = insn(31, 12)
 
   // Debug instruction
-  io.x31 := insn;
+  io.x31 := reg_file.io.rs1_data;
   if(sim)
   {
     io.valid_x31.get := true.B;
   }
 
-  //io.ibus.wdata
-  //io.ibus.be
-
   io.dbus.addr := 0.U;
   io.dbus.wdata := 0.U;
   io.dbus.be := VecInit(false.B,false.B,false.B,false.B)