30 lines
685 B
Scala
30 lines
685 B
Scala
package projet
|
|
|
|
import chisel3._
|
|
|
|
class RegFile(sim: Boolean = false) extends Module {
|
|
val io = IO(new Bundle {
|
|
val rs1_addr = Input(UInt(5.W))
|
|
val rs2_addr = Input(UInt(5.W))
|
|
val rd_addr = Input(UInt(5.W))
|
|
val rd_data = Input(UInt(32.W))
|
|
val we = Input(Bool())
|
|
val rs1_data = Output(UInt(32.W))
|
|
val rs2_data = Output(UInt(32.W))
|
|
})
|
|
|
|
val regs = Mem(32, UInt(32.W))
|
|
|
|
if (sim) {
|
|
when(reset.asBool) {
|
|
regs(0.U) := 0.U
|
|
}
|
|
}
|
|
|
|
when(io.we && io.rd_addr =/= 0.U) {
|
|
regs(io.rd_addr) := io.rd_data
|
|
}
|
|
io.rs1_data := regs(io.rs1_addr)
|
|
io.rs2_data := regs(io.rs2_addr)
|
|
}
|