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Stage 8: all tests passing

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This commit is contained in:
Albin Chaboissier
2025-11-07 15:27:15 +01:00
parent c88662403e
commit e83e7c11c1
3 changed files with 20 additions and 11 deletions
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12
src/main/scala/projet/ControlUnit.scala
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@@ -124,10 +124,14 @@ class ControlUnit() extends Module {
// J instructions
is(OpCode.JAL) {
io.alu_opcode := AluOpCode.Add
io.alu_opcode := AluOpCode.Add // ALU is unused
io.reg_file_we := true.B // Write to regfile
io.mux_rega_pc := false.B // Send PC to ALU A
io.mux_regb_imm := false.B; // Send imm to ALU B
io.mux_writeback_pc := false.B;
// io.mux_rega_pc := false.B // Send PC to ALU A
// io.mux_regb_imm := false.B; // Send imm to ALU B
io.is_jump := true.B
io.mux_incrpc4_imm := false.B; // Send the immediate in PC
io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
@@ -145,7 +149,7 @@ class ControlUnit() extends Module {
io.mux_rega_pc := true.B // Send rs1 to ALU A
io.mux_regb_imm := false.B; // Send imm to ALU B
io.mux_alu_imm := false.B; // Send alu out to write back line
io.mux_alu_imm := true.B; // Send alu out to write back line
io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
io.optype := OpType.I
}