diff --git a/bench/tests/op/jal.s b/bench/tests/op/jal.s
index d25278a..1342c97 100644
--- a/bench/tests/op/jal.s
+++ b/bench/tests/op/jal.s
@@ -1,12 +1,17 @@
-# expected: 00000004, 0000008, 0000000C
+# expected: 00000004, 0000008, 00000014, 0000000B
     .text
 _start:
     jal x31, step1
 step1:
     jal x31, step2
+step4:
+    addi x31, x0, 0x00B
+    jal x0, finish
 step2:
     jal x31, step3
 step3:
+    jal x0, step4
+    addi x31, x0, 0x00A # This instruction should never be executed
+finish:
     nop
 
-
diff --git a/bench/tests/op/jalr.s b/bench/tests/op/jalr.s
index 1ad6ad1..4cb4d55 100644
--- a/bench/tests/op/jalr.s
+++ b/bench/tests/op/jalr.s
@@ -1,15 +1,15 @@
-# expected: 000000BA, 0000018, 0000000A
+# expected: 000000BA, 000001C, 0000000A
     .text
 _start:
     jal x1, step1
-    add x31, x0, 0x00A
+    addi x31, x0, 0x00A
     jal x0, finish
 step1:
     jal x2, step2
-    add x31, x0, 0x0AB # This instruction should never be executed
-    add x31, x0, 0x0BA
+    addi x31, x0, 0x0AB # This instruction should never be executed
+    addi x31, x0, 0x0BA
     jalr x31, 0(x1) # Check if return address is written to x31
 step2:
-    jalr x0, 1(x2) # return to step1, but 1 further
+    jalr x0, 4(x2) # return to step1, but 1 further
 finish:
     nop
diff --git a/src/main/scala/projet/ControlUnit.scala b/src/main/scala/projet/ControlUnit.scala
index e4dc995..841d2b5 100644
--- a/src/main/scala/projet/ControlUnit.scala
+++ b/src/main/scala/projet/ControlUnit.scala
@@ -124,10 +124,14 @@ class ControlUnit() extends Module {
 
         // J instructions
         is(OpCode.JAL) {
-            io.alu_opcode := AluOpCode.Add
+            io.alu_opcode := AluOpCode.Add // ALU is unused
+
             io.reg_file_we := true.B // Write to regfile
-            io.mux_rega_pc := false.B // Send PC to ALU A
-            io.mux_regb_imm := false.B; // Send imm to ALU B
+            io.mux_writeback_pc := false.B;
+
+            // io.mux_rega_pc := false.B // Send PC to ALU A
+            // io.mux_regb_imm := false.B; // Send imm to ALU B
+
             io.is_jump := true.B
             io.mux_incrpc4_imm := false.B; // Send the immediate in PC
             io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
@@ -145,7 +149,7 @@ class ControlUnit() extends Module {
             io.mux_rega_pc := true.B // Send rs1 to ALU A
             io.mux_regb_imm := false.B; // Send imm to ALU B
 
-            io.mux_alu_imm := false.B; // Send alu out to write back line
+            io.mux_alu_imm := true.B; // Send alu out to write back line
             io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
             io.optype := OpType.I
         }