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Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

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This commit is contained in:
Albin Chaboissier
2025-11-15 00:57:59 +01:00
parent 0c377a1380
commit e35f2a4242
8 changed files with 75 additions and 62 deletions
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6
src/main/scala/projet/Rv64i.scala
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@@ -101,13 +101,15 @@ class Rv64i(sim: Boolean = true) extends Module {
);
val rs1_data =
Mux(
rs1_index === reg_rd_index && rs1_index =/= 0.U,
rs1_index === reg_rd_index && rs1_index =/= 0.U
&& Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
writeback_line,
reg_file.io.rs1_data
)
val rs2_data =
Mux(
rs2_index === reg_rd_index && rs2_index =/= 0.U,
rs2_index === reg_rd_index && rs2_index =/= 0.U
&& Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
writeback_line,
reg_file.io.rs2_data
)