diff --git a/bench/programs_rust/Cargo.toml b/bench/programs_rust/Cargo.toml
index a22a47c..968f0ce 100644
--- a/bench/programs_rust/Cargo.toml
+++ b/bench/programs_rust/Cargo.toml
@@ -6,7 +6,7 @@ members = ["fpga-lib", "fpga-lib-macros", "hello-rust"]
 panic = "abort"
 codegen-units = 1 # better optimizations
 lto = true # better optimizations
-strip = true
+strip = false
 opt-level = "z"
 
 [profile.dev]
diff --git a/bench/programs_rust/fpga-lib/src/vga.rs b/bench/programs_rust/fpga-lib/src/vga.rs
index baa0617..fbe790c 100644
--- a/bench/programs_rust/fpga-lib/src/vga.rs
+++ b/bench/programs_rust/fpga-lib/src/vga.rs
@@ -46,10 +46,12 @@ impl VGA
     {
         let c = if (c as u8 > b'~') || ((c as u8) < b' ')
         {
+            unsafe { Self::write_pixel_unsafe(x, y, RED) };
             b'/' - b' '
         }
         else
         {
+            unsafe { Self::write_pixel_unsafe(x, y, GREEN) };
             c as u8 - b' '
         };
 
@@ -64,12 +66,12 @@ impl VGA
                 let xx = x + i;
                 let yy = y + j;
 
-                if xx < (WIDTH as u16)
-                    && yy < (HEIGHT as u16)
-                    && unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) }
-                //if unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) }
+                // if xx < (WIDTH as u16)
+                //     && yy < (HEIGHT as u16)
+                //     && unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) }
+                if unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) }
                 {
-                    unsafe { Self::write_pixel_unsafe(xx, yy, color) }
+                    //     //unsafe { Self::write_pixel_unsafe(xx, yy, color) }
                 }
             }
         }
diff --git a/bench/programs_rust/hello-rust/src/main.rs b/bench/programs_rust/hello-rust/src/main.rs
index 043ab6a..2827ebb 100644
--- a/bench/programs_rust/hello-rust/src/main.rs
+++ b/bench/programs_rust/hello-rust/src/main.rs
@@ -11,37 +11,38 @@ use fpga_lib::{
 
 panic_handler! {}
 
+#[inline(never)]
+pub fn magic(x: &mut u16, y: &mut u16, z: &mut bool, i: u16, j: u16)
+{
+    if *x > i && *y < 198 && *z
+    {
+        unsafe { VGA::write_pixel_unsafe(i, j, GREEN) };
+    }
+    else
+    {
+        unsafe { VGA::write_pixel_unsafe(i, j, RED) };
+    }
+
+    //*x += 1;
+    *y -= 1;
+}
+
 #[unsafe(no_mangle)]
 pub extern "C" fn main() -> !
 {
-    // X31::write_const::<0xdead1ffffffff>();
-    // let test = X31::read() + 10;
-    //unsafe {
-    // asm!(
-    //     "add x31, x0, x0",
-    //     "add x31, x0, {}", in(reg) test
-    // );
-    //
-    // for i in 0..100
-    // {
-    //     VGA::write_pixel_unsafe(i, i, WHITE);
-    // }
-    //let c = core::hint::black_box('S');
-    let c = core::hint::black_box('S');
-    //unsafe { VGA::draw_char(10, 10, c, RED) };
-    //unsafe { VGA::draw_string(3, 3, "{Skibidi toilet !!}", GREEN) };
-    //}
+    let mut x = core::hint::black_box(100u16);
+    let mut y = core::hint::black_box(192);
+    let mut z = core::hint::black_box(true);
 
-    // for i in 0..2
-    // {
-    //     unsafe { VGA::draw_char(0 + i as u16 * FONT_WIDTH as u16, 0, c, RED) };
-    // }
+    let x = core::hint::black_box(&mut x);
+    let y = core::hint::black_box(&mut y);
+    let z = core::hint::black_box(&mut z);
 
-    // unsafe { VGA::draw_char(0, 0, c, RED) };
-    // unsafe { VGA::draw_char(1, 0, c, RED) };
+    for i in 0..(*x)
+    {
+        magic(x, y, z, i, i);
+    }
 
-    unsafe { VGA::draw_char(1, 0, c, RED) };
-    unsafe { VGA::draw_char(1, 0, c, GREEN) };
     // if (c as u8 > b'~') || ((c as u8) < b' ')
     // {
     //     X31::write_const::<0x01>();
diff --git a/bench/tests/op/lh.s b/bench/tests/op/lh.s
index 6d297a3..eb1df43 100644
--- a/bench/tests/op/lh.s
+++ b/bench/tests/op/lh.s
@@ -1,12 +1,17 @@
-# expected: FFFFFFFFFFFFF1BC, FFFFFFFFFFFFF1BC
+# expected: FFFFFFFFFFFFCDEF, FFFFFFFFFFFF89AB, 4567, 0123
+
     .text
 _start:
-    lui x1, 0xF
-    ori x1, x1, 0x1BC
-    sh x1, 100(x0)
-    lh x31, 100(x0)
+    li x2, 0x10100
+
+    li x1, 0x0123456789ABCDEF
+    sd x1, 0(x2)
+
+    lh x31, 0(x2)
+
+    lh x31, 2(x2)
+
+    lh x31, 4(x2)
+
+    lh x31, 6(x2)
 
-    lui x1, 0xF
-    ori x1, x1, 0x1BC
-    sh x1, 106(x0)
-    lh x31, 106(x0)
diff --git a/bench/tests/op/lw.s b/bench/tests/op/lw.s
index 71887bc..5ff210c 100644
--- a/bench/tests/op/lw.s
+++ b/bench/tests/op/lw.s
@@ -1,11 +1,16 @@
-# expected: 123451BC, FFFFFFFFF0000000
+# expected: 123451BC, 123451BC, FFFFFFFFF0000000
     .text
 _start:
-    lui x1, 0x12345
-    ori x1, x1, 0x1BC
-    sw x1, 100(x0)
-    lw x31, 100(x0)
+    li x2, 0x11000
+
+    li x1, 0x123451BC
+    sw x1, 100(x2)
+    lw x31, 100(x2)
+
+    li x1, 0x123451BC
+    sw x1, 104(x2)
+    lw x31, 104(x2)
 
     li x1, 0x00000000F0000000
-    sw x1, 100(x0)
-    lw x31, 100(x0)
+    sw x1, 100(x2)
+    lw x31, 100(x2)
diff --git a/src/main/scala/projet/DMem.scala b/src/main/scala/projet/DMem.scala
index 956e2dd..3b73b54 100644
--- a/src/main/scala/projet/DMem.scala
+++ b/src/main/scala/projet/DMem.scala
@@ -47,19 +47,15 @@ class DMem extends Module {
                     (io.addr(2) * 32.U + io.addr(1) * 16.U + io.addr(0) * 8.U)
             }
             is(DMemSize.Half) {
-                bytes_enabled(
-                    (io.addr(2) * 4.U(3.W) + io.addr(1) * 2.U(3.W))(2, 0)
-                ) := true.B
-                bytes_enabled(
-                    (io.addr(2) * 4.U(3.W) + io.addr(1) * 2.U(3.W))(2, 0) + 1.U
-                ) := true.B
-                data := io.data_in << (io.addr(2) * 32.U + io.addr(1) * 16.U)
+                bytes_enabled(io.addr(2, 0)) := true.B
+                bytes_enabled(io.addr(2, 0) + 1.U) := true.B
+                data := io.data_in << (io.addr(2, 0) * 8.U)
             }
             is(DMemSize.Word) {
-                bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0)) := true.B
-                bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 1.U) := true.B
-                bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 2.U) := true.B
-                bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 3.U) := true.B
+                bytes_enabled(io.addr(2, 0)) := true.B
+                bytes_enabled(io.addr(2, 0) + 1.U) := true.B
+                bytes_enabled(io.addr(2, 0) + 2.U) := true.B
+                bytes_enabled(io.addr(2, 0) + 3.U) := true.B
                 data := io.data_in << (io.addr(2) * 32.U)
             }
             is(DMemSize.Long) {
@@ -99,7 +95,7 @@ class DMem extends Module {
 
             is(DMemSize.Half) {
                 val dout = (io.dbus.rdata >>
-                    (read_addr(2) * 32.U + read_addr(1) * 16.U)) & 0xffff.U;
+                    (read_addr(2, 0) * 8.U)) & 0xffff.U;
                 io.data_out := dout | Mux(
                     read_sign_extend,
                     Fill(48, dout(15)) << 16.U,
diff --git a/src/main/scala/projet/RegFile.scala b/src/main/scala/projet/RegFile.scala
index fa2910f..e07f607 100644
--- a/src/main/scala/projet/RegFile.scala
+++ b/src/main/scala/projet/RegFile.scala
@@ -20,7 +20,9 @@ class RegFile(sim: Boolean = false) extends Module {
 
     if (sim) {
         when(reset.asBool) {
-            regs(0.U) := 0.U
+            for (i <- 0 to 32) {
+                regs(i.U) := 0.U
+            }
         }
     }
 
diff --git a/src/main/scala/projet/Rv64i.scala b/src/main/scala/projet/Rv64i.scala
index 8f48553..7a4fa58 100644
--- a/src/main/scala/projet/Rv64i.scala
+++ b/src/main/scala/projet/Rv64i.scala
@@ -101,13 +101,15 @@ class Rv64i(sim: Boolean = true) extends Module {
     );
     val rs1_data =
         Mux(
-            rs1_index === reg_rd_index && rs1_index =/= 0.U,
+            rs1_index === reg_rd_index && rs1_index =/= 0.U
+                && Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
             writeback_line,
             reg_file.io.rs1_data
         )
     val rs2_data =
         Mux(
-            rs2_index === reg_rd_index && rs2_index =/= 0.U,
+            rs2_index === reg_rd_index && rs2_index =/= 0.U
+                && Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
             writeback_line,
             reg_file.io.rs2_data
         )