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Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

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This commit is contained in:
Albin Chaboissier
2025-11-15 00:57:59 +01:00
parent 0c377a1380
commit e35f2a4242
8 changed files with 75 additions and 62 deletions
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20
src/main/scala/projet/DMem.scala
View File

@@ -47,19 +47,15 @@ class DMem extends Module {
(io.addr(2) * 32.U + io.addr(1) * 16.U + io.addr(0) * 8.U)
}
is(DMemSize.Half) {
bytes_enabled(
(io.addr(2) * 4.U(3.W) + io.addr(1) * 2.U(3.W))(2, 0)
) := true.B
bytes_enabled(
(io.addr(2) * 4.U(3.W) + io.addr(1) * 2.U(3.W))(2, 0) + 1.U
) := true.B
data := io.data_in << (io.addr(2) * 32.U + io.addr(1) * 16.U)
bytes_enabled(io.addr(2, 0)) := true.B
bytes_enabled(io.addr(2, 0) + 1.U) := true.B
data := io.data_in << (io.addr(2, 0) * 8.U)
}
is(DMemSize.Word) {
bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0)) := true.B
bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 1.U) := true.B
bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 2.U) := true.B
bytes_enabled((io.addr(2) * 4.U(3.W))(2, 0) + 3.U) := true.B
bytes_enabled(io.addr(2, 0)) := true.B
bytes_enabled(io.addr(2, 0) + 1.U) := true.B
bytes_enabled(io.addr(2, 0) + 2.U) := true.B
bytes_enabled(io.addr(2, 0) + 3.U) := true.B
data := io.data_in << (io.addr(2) * 32.U)
}
is(DMemSize.Long) {
@@ -99,7 +95,7 @@ class DMem extends Module {
is(DMemSize.Half) {
val dout = (io.dbus.rdata >>
(read_addr(2) * 32.U + read_addr(1) * 16.U)) & 0xffff.U;
(read_addr(2, 0) * 8.U)) & 0xffff.U;
io.data_out := dout | Mux(
read_sign_extend,
Fill(48, dout(15)) << 16.U,

4
src/main/scala/projet/RegFile.scala
View File

@@ -20,7 +20,9 @@ class RegFile(sim: Boolean = false) extends Module {
if (sim) {
when(reset.asBool) {
regs(0.U) := 0.U
for (i <- 0 to 32) {
regs(i.U) := 0.U
}
}
}

6
src/main/scala/projet/Rv64i.scala
View File

@@ -101,13 +101,15 @@ class Rv64i(sim: Boolean = true) extends Module {
);
val rs1_data =
Mux(
rs1_index === reg_rd_index && rs1_index =/= 0.U,
rs1_index === reg_rd_index && rs1_index =/= 0.U
&& Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
writeback_line,
reg_file.io.rs1_data
)
val rs2_data =
Mux(
rs2_index === reg_rd_index && rs2_index =/= 0.U,
rs2_index === reg_rd_index && rs2_index =/= 0.U
&& Delay.Delay(control_unit.io.reg_file_we, 1, false.B),
writeback_line,
reg_file.io.rs2_data
)