Corrects critical mistake where core tried to bypass even if previous instruction did not write-back

bench/tests/op/lh.s

@@ -1,12 +1,17 @@
-# expected: FFFFFFFFFFFFF1BC, FFFFFFFFFFFFF1BC
+# expected: FFFFFFFFFFFFCDEF, FFFFFFFFFFFF89AB, 4567, 0123
+
     .text
 _start:
-    lui x1, 0xF
-    ori x1, x1, 0x1BC
-    sh x1, 100(x0)
-    lh x31, 100(x0)
+    li x2, 0x10100
+
+    li x1, 0x0123456789ABCDEF
+    sd x1, 0(x2)
+
+    lh x31, 0(x2)
+
+    lh x31, 2(x2)
+
+    lh x31, 4(x2)
+
+    lh x31, 6(x2)
 
-    lui x1, 0xF
-    ori x1, x1, 0x1BC
-    sh x1, 106(x0)
-    lh x31, 106(x0)

bench/tests/op/lw.s

@@ -1,11 +1,16 @@
-# expected: 123451BC, FFFFFFFFF0000000
+# expected: 123451BC, 123451BC, FFFFFFFFF0000000
     .text
 _start:
-    lui x1, 0x12345
-    ori x1, x1, 0x1BC
-    sw x1, 100(x0)
-    lw x31, 100(x0)
+    li x2, 0x11000
+
+    li x1, 0x123451BC
+    sw x1, 100(x2)
+    lw x31, 100(x2)
+
+    li x1, 0x123451BC
+    sw x1, 104(x2)
+    lw x31, 104(x2)
 
     li x1, 0x00000000F0000000
-    sw x1, 100(x0)
-    lw x31, 100(x0)
+    sw x1, 100(x2)
+    lw x31, 100(x2)