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Ups frequency to 80Mhz : unstable behaviour

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This commit is contained in:
Albin Chaboissier
2025-11-16 16:45:00 +01:00
parent dbe0a488f3
commit c0b4311458
5 changed files with 181 additions and 100 deletions
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145
src/main/scala/projet/Alu.scala
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@@ -65,19 +65,19 @@ class Alu extends Module {
val in_computation = RegInit(false.B)
// Division
val divider = Module(new Divider(64, Constants.DIVISION_CYCLES_COUNT))
divider.io.word_mode := io.word_mode
divider.io.dividend := op_a_unsigned
divider.io.divisor := op_b_unsigned
divider.io.start := false.B
def div_by_zero() = {
when(io.word_mode) {
out := (-1).S(32.W).asUInt
}.otherwise {
out := (-1).S(64.W).asUInt
}
}
// // Division
// val divider = Module(new Divider(64, Constants.DIVISION_CYCLES_COUNT))
// divider.io.word_mode := io.word_mode
// divider.io.dividend := op_a_unsigned
// divider.io.divisor := op_b_unsigned
// divider.io.start := false.B
// def div_by_zero() = {
// when(io.word_mode) {
// out := (-1).S(32.W).asUInt
// }.otherwise {
// out := (-1).S(64.W).asUInt
// }
// }
// Multiplication
val multiplication_res = op_a * op_b // Mul non signée
@@ -123,54 +123,54 @@ class Alu extends Module {
out := multiplication_high;
}
is(Div) {
when(op_b === 0.U) {
div_by_zero()
}.elsewhen(op_a_sign ^ op_b_sign) {
out := Utils.two_complement(divider.io.quotient, io.word_mode)
}.otherwise {
out := divider.io.quotient
}
}
is(Divu) {
divider.io.dividend := op_a
divider.io.divisor := op_b
when(op_b === 0.U) {
div_by_zero()
}.otherwise { out := divider.io.quotient; }
}
is(Rem) {
when(op_b === 0.U) {
out := op_a
}.elsewhen(
op_a_sign && !op_b_sign && divider.io.remainder =/= 0.U
) {
out := op_b - divider.io.remainder
}.elsewhen(
!op_a_sign && op_b_sign && divider.io.remainder =/= 0.U
) {
out := Utils.two_complement(
Utils.two_complement(op_b) - divider.io.remainder,
io.word_mode
)
}.elsewhen(op_a_sign && op_b_sign) {
out := Utils.two_complement(divider.io.remainder, io.word_mode)
}.otherwise {
out := divider.io.remainder
}
}
is(Remu) {
divider.io.dividend := op_a
divider.io.divisor := op_b
when(op_b === 0.U) {
out := op_a
}.otherwise {
out := divider.io.remainder
}
}
// is(Div) {
// when(op_b === 0.U) {
// div_by_zero()
// }.elsewhen(op_a_sign ^ op_b_sign) {
// out := Utils.two_complement(divider.io.quotient, io.word_mode)
// }.otherwise {
// out := divider.io.quotient
// }
// }
//
// is(Divu) {
// divider.io.dividend := op_a
// divider.io.divisor := op_b
// when(op_b === 0.U) {
// div_by_zero()
// }.otherwise { out := divider.io.quotient; }
// }
//
// is(Rem) {
// when(op_b === 0.U) {
// out := op_a
// }.elsewhen(
// op_a_sign && !op_b_sign && divider.io.remainder =/= 0.U
// ) {
// out := op_b - divider.io.remainder
// }.elsewhen(
// !op_a_sign && op_b_sign && divider.io.remainder =/= 0.U
// ) {
// out := Utils.two_complement(
// Utils.two_complement(op_b) - divider.io.remainder,
// io.word_mode
// )
// }.elsewhen(op_a_sign && op_b_sign) {
// out := Utils.two_complement(divider.io.remainder, io.word_mode)
// }.otherwise {
// out := divider.io.remainder
// }
// }
//
// is(Remu) {
// divider.io.dividend := op_a
// divider.io.divisor := op_b
// when(op_b === 0.U) {
// out := op_a
// }.otherwise {
// out := divider.io.remainder
// }
// }
is(And) {
out := op_a & op_b;
@@ -231,17 +231,18 @@ class Alu extends Module {
}
}
switch(io.opcode) {
is(Div, Divu, Rem, Remu) {
when(!in_computation) {
divider.io.start := true.B
in_computation := true.B
}.elsewhen(divider.io.ready) {
io.should_stop_stall := true.B
in_computation := false.B
}
}
}
// switch(io.opcode) {
// is(Div, Divu, Rem, Remu) {
// when(!in_computation) {
// divider.io.start := true.B
// in_computation := true.B
// }.elsewhen(divider.io.ready) {
// io.should_stop_stall := true.B
// in_computation := false.B
// }
// }
// }
//
// Special overflow cases for Div and Rem
when(