Modifies alu for branching instructions

src/main/scala/projet/Alu.scala

@@ -6,7 +6,8 @@ import chisel3.util.is
 
 object AluOpCode extends ChiselEnum {
     val Add, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
-        LessThanSigned, LessThanUnsigned = Value
+        LessThanSigned, LessThanUnsigned, GreaterEqualSigned, GreaterEqualUnsigned,
+        Equal = Value
 }
 
 class Alu extends Module {
@@ -17,10 +18,11 @@ class Alu extends Module {
         val b = Input(UInt(32.W))
         val out = Output(UInt(32.W))
         val opcode = Input(AluOpCode())
+        val comp_result = Output(Bool())
     })
 
     io.out := 0.U;
-
+    io.flags := false.B;
     switch(io.opcode) {
         is(Add) {
             io.out := io.a + io.b;
@@ -52,11 +54,31 @@ class Alu extends Module {
         }
 
         is(LessThanUnsigned) {
-            io.out := io.a < io.b
+            val less_than = io.a < io.b;
+            io.out := less_than;
+            io.comp_result := less_than;
         }
 
         is(LessThanSigned) {
-            io.out := io.a.asSInt < io.b.asSInt
+            val less_than := io.a.asSInt < io.b.asSInt
+            io.out := less_than
+            io.comp_result := less_than;
+        }
+        
+        is(GreaterEqualUnsigned) {
+            val geq_than = io.a >== io.b;
+            io.out := geq_than
+            io.comp_result := geq_than;
+        }
+
+        is(GreaterEqualSigned) {
+          val geq_than := io.a.asSInt >== io.b.asSInt
+            io.out := geq_than
+            io.comp_result := geq_than;
+        }
+
+        is(Equal) {
+            io.comp_result := io.& === io.b;
         }
     }