From a8977786050d90adc14617fff594df8a7de1bcb9 Mon Sep 17 00:00:00 2001 From: Albin Chaboissier Date: Fri, 7 Nov 2025 17:04:05 +0100 Subject: [PATCH] Modifies alu for branching instructions --- src/main/scala/projet/Alu.scala | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/main/scala/projet/Alu.scala b/src/main/scala/projet/Alu.scala index 75717bb..560e6e9 100644 --- a/src/main/scala/projet/Alu.scala +++ b/src/main/scala/projet/Alu.scala @@ -6,7 +6,8 @@ import chisel3.util.is object AluOpCode extends ChiselEnum { val Add, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight, - LessThanSigned, LessThanUnsigned = Value + LessThanSigned, LessThanUnsigned, GreaterEqualSigned, GreaterEqualUnsigned, + Equal = Value } class Alu extends Module { @@ -17,10 +18,11 @@ class Alu extends Module { val b = Input(UInt(32.W)) val out = Output(UInt(32.W)) val opcode = Input(AluOpCode()) + val comp_result = Output(Bool()) }) io.out := 0.U; - + io.flags := false.B; switch(io.opcode) { is(Add) { io.out := io.a + io.b; @@ -52,11 +54,31 @@ class Alu extends Module { } is(LessThanUnsigned) { - io.out := io.a < io.b + val less_than = io.a < io.b; + io.out := less_than; + io.comp_result := less_than; } is(LessThanSigned) { - io.out := io.a.asSInt < io.b.asSInt + val less_than := io.a.asSInt < io.b.asSInt + io.out := less_than + io.comp_result := less_than; + } + + is(GreaterEqualUnsigned) { + val geq_than = io.a >== io.b; + io.out := geq_than + io.comp_result := geq_than; + } + + is(GreaterEqualSigned) { + val geq_than := io.a.asSInt >== io.b.asSInt + io.out := geq_than + io.comp_result := geq_than; + } + + is(Equal) { + io.comp_result := io.& === io.b; } }