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Corrects critical mistake in JAL, corrects VgaIp

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This commit is contained in:
Albin Chaboissier
2025-11-13 16:53:04 +01:00
parent 1d0aa7db4b
commit 84569017c8
2 changed files with 5 additions and 4 deletions
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2
src/main/scala/projet/ImmediateDecoder.scala
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@@ -22,7 +22,7 @@ class ImmediateDecoder extends Module {
val imm_i = Cat(Fill(52, io.instruction(31)), io.instruction(31, 20)); val imm_i = Cat(Fill(52, io.instruction(31)), io.instruction(31, 20));
val imm_ir = io.instruction(25, 20); val imm_ir = io.instruction(25, 20);
val imm_j = Cat( val imm_j = Cat(
Fill(33, io.instruction(31)), Fill(43, io.instruction(31)),
io.instruction(31), io.instruction(31),
io.instruction(19, 12), io.instruction(19, 12),
io.instruction(20), io.instruction(20),

7
src/main/scala/projet/VgaIp.scala
View File

@@ -19,7 +19,7 @@ class VgaIp extends Module {
io.hs := RegNext(sync.io.hsync) io.hs := RegNext(sync.io.hsync)
io.vs := RegNext(sync.io.vsync) io.vs := RegNext(sync.io.vsync)
val img_sync = RegNext(sync.io.img) val img_sync = RegNext(sync.io.img)
val index = RegNext(sync.io.x(3, 1)) val index = RegNext(sync.io.x(2, 1))
io.bus.en := true.B io.bus.en := true.B
io.bus.be := VecInit( io.bus.be := VecInit(
@@ -37,10 +37,11 @@ class VgaIp extends Module {
// Adresse mot dans la ram vidéo // Adresse mot dans la ram vidéo
io.bus.addr := addr(13, 0) ## 0.U(3.W) io.bus.addr := addr(13, 0) ## 0.U(3.W)
val word32 = io.bus.rdata >> (RegNext(sync.io.x(3)) * 32.U)
val pixel = MuxCase( val pixel = MuxCase(
0.U, 0.U,
(0 until 8).map { i => (0 until 4).map { i =>
(index === i.U) -> io.bus.rdata(8 * (7 - i) + 7, 8 * (7 - i)) (index === i.U) -> word32(8 * (3 - i) + 7, 8 * (3 - i))
} }
) )