diff --git a/src/main/scala/projet/ImmediateDecoder.scala b/src/main/scala/projet/ImmediateDecoder.scala
index 28e7a42..48c1c67 100644
--- a/src/main/scala/projet/ImmediateDecoder.scala
+++ b/src/main/scala/projet/ImmediateDecoder.scala
@@ -22,7 +22,7 @@ class ImmediateDecoder extends Module {
     val imm_i = Cat(Fill(52, io.instruction(31)), io.instruction(31, 20));
     val imm_ir = io.instruction(25, 20);
     val imm_j = Cat(
-        Fill(33, io.instruction(31)),
+        Fill(43, io.instruction(31)),
         io.instruction(31),
         io.instruction(19, 12),
         io.instruction(20),
diff --git a/src/main/scala/projet/VgaIp.scala b/src/main/scala/projet/VgaIp.scala
index 33c284e..ed1363d 100644
--- a/src/main/scala/projet/VgaIp.scala
+++ b/src/main/scala/projet/VgaIp.scala
@@ -19,7 +19,7 @@ class VgaIp extends Module {
         io.hs := RegNext(sync.io.hsync)
         io.vs := RegNext(sync.io.vsync)
         val img_sync = RegNext(sync.io.img)
-        val index = RegNext(sync.io.x(3, 1))
+        val index = RegNext(sync.io.x(2, 1))
 
         io.bus.en := true.B
         io.bus.be := VecInit(
@@ -37,10 +37,11 @@ class VgaIp extends Module {
         // Adresse mot dans la ram vidéo
         io.bus.addr := addr(13, 0) ## 0.U(3.W)
 
+        val word32 = io.bus.rdata >> (RegNext(sync.io.x(3)) * 32.U)
         val pixel = MuxCase(
             0.U,
-            (0 until 8).map { i =>
-                (index === i.U) -> io.bus.rdata(8 * (7 - i) + 7, 8 * (7 - i))
+            (0 until 4).map { i =>
+                (index === i.U) -> word32(8 * (3 - i) + 7, 8 * (3 - i))
             }
         )