Implements (mostly untested) rv64i)

This commit is contained in:
2025-11-12 18:02:14 +01:00
parent 8ac17f20fe
commit 7bb8b993ae
8 changed files with 158 additions and 18 deletions

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@@ -47,64 +47,69 @@ class Alu extends Module {
switch(io.opcode) {
is(Add) {
out := io.a + io.b;
out := op_a + op_b;
}
is(Sub) {
out := io.a - io.b;
out := op_a - op_b;
}
is(And) {
out := io.a & io.b;
out := op_a & op_b;
}
is(Or) {
out := io.a | io.b;
out := op_a | op_b;
}
is(Xor) {
out := io.a ^ io.b;
out := op_a ^ op_b;
}
is(ShiftLeft) {
out := io.a << io.b(5, 0);
out := op_a << op_b(5, 0);
}
is(ShiftRight) {
out := io.a >> io.b(5, 0);
out := op_a >> op_b(5, 0);
}
is(ShiftArithmeticRight) {
// >> means arithmetic shift for SInts
out := (io.a.asSInt >> io.b(5, 0)).asUInt;
out := (op_a.asSInt >> op_b(5, 0)).asUInt;
// Signed shift on 32bit requires careful handling
when(io.word_mode) {
out := (op_a(31, 0).asSInt >> op_b(5, 0)).asUInt
}
}
is(LessThanUnsigned) {
val less_than = io.a < io.b;
val less_than = op_a < op_b;
out := less_than;
io.comp_result := less_than;
}
is(LessThanSigned) {
val less_than = io.a.asSInt < io.b.asSInt
val less_than = op_a.asSInt < op_b.asSInt
out := less_than
io.comp_result := less_than;
}
is(GreaterEqualUnsigned) {
val geq_than = io.a >= io.b;
val geq_than = op_a >= op_b;
out := geq_than
io.comp_result := geq_than;
}
is(GreaterEqualSigned) {
val geq_than = io.a.asSInt >= io.b.asSInt
val geq_than = op_a.asSInt >= op_b.asSInt
out := geq_than
io.comp_result := geq_than;
}
is(Equal) {
io.comp_result := io.a === io.b;
io.comp_result := op_a === op_b;
}
}