117 lines
2.6 KiB
Scala
117 lines
2.6 KiB
Scala
package projet
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import chisel3._
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import chisel3.util.switch
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import chisel3.util.is
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object AluOpCode extends ChiselEnum {
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val Add, Sub, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
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LessThanSigned, LessThanUnsigned, GreaterEqualSigned,
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GreaterEqualUnsigned, Equal = Value
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}
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class Alu extends Module {
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import AluOpCode._
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val io = IO(new Bundle {
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val a = Input(UInt(64.W))
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val b = Input(UInt(64.W))
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val out = Output(UInt(64.W))
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val opcode = Input(AluOpCode())
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val comp_result = Output(Bool())
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// ~~ Rv64i ~~
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// If word_mode is enabled, operations are performed
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// on 32-bit-truncated inputs and then sign extended to 64bits
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val word_mode = Input(Bool())
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})
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io.out := 0.U;
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io.comp_result := false.B;
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val out = WireInit(0.U(64.W))
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val op_a = WireInit(0.U(64.W))
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val op_b = WireInit(0.U(64.W))
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// Defaults
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op_a := io.a
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op_b := io.b
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io.out := out
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// Truncate operands, sext result
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when(io.word_mode) {
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op_a := io.a(31, 0)
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op_b := io.b(31, 0)
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io.out := SignExtend.Sext(out(31, 0), 64)
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}
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switch(io.opcode) {
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is(Add) {
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out := op_a + op_b;
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}
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is(Sub) {
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out := op_a - op_b;
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}
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is(And) {
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out := op_a & op_b;
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}
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is(Or) {
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out := op_a | op_b;
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}
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is(Xor) {
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out := op_a ^ op_b;
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}
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is(ShiftLeft) {
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out := op_a << op_b(5, 0);
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}
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is(ShiftRight) {
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out := op_a >> op_b(5, 0);
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}
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is(ShiftArithmeticRight) {
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// >> means arithmetic shift for SInts
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out := (op_a.asSInt >> op_b(5, 0)).asUInt;
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// Signed shift on 32bit requires careful handling
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when(io.word_mode) {
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out := (op_a(31, 0).asSInt >> op_b(5, 0)).asUInt
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}
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}
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is(LessThanUnsigned) {
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val less_than = op_a < op_b;
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out := less_than;
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io.comp_result := less_than;
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}
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is(LessThanSigned) {
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val less_than = op_a.asSInt < op_b.asSInt
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out := less_than
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io.comp_result := less_than;
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}
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is(GreaterEqualUnsigned) {
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val geq_than = op_a >= op_b;
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out := geq_than
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io.comp_result := geq_than;
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}
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is(GreaterEqualSigned) {
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val geq_than = op_a.asSInt >= op_b.asSInt
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out := geq_than
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io.comp_result := geq_than;
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}
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is(Equal) {
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io.comp_result := op_a === op_b;
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}
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}
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}
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