Stage 11: Passing tests

bench/tests/op/lb.s

@@ -0,0 +1,12 @@
+# expected: FFFFFFFB, FFFFFFFB
+    .text
+_start:
+    addi x1, x0, 0x0FB
+    nop # Next instruction depends on previous register op
+    sb x1, 100(x0)
+    lb x31, 100(x0)
+
+    addi x1, x0, 0x0FB
+    nop # Next instruction depends on previous register op
+    sb x1, 106(x0)
+    lb x31, 106(x0)

bench/tests/op/lbu.s

@@ -0,0 +1,12 @@
+# expected: 000000FB, 000000FB
+    .text
+_start:
+    addi x1, x0, 0x0FB
+    nop # Next instruction depends on previous register op
+    sb x1, 100(x0)
+    lbu x31, 100(x0)
+
+    addi x1, x0, 0x0FB
+    nop # Next instruction depends on previous register op
+    sb x1, 106(x0)
+    lbu x31, 106(x0)

bench/tests/op/lh.s

@@ -0,0 +1,16 @@
+# expected: FFFFF1BC, FFFFF1BC
+    .text
+_start:
+    lui x1, 0xF
+    nop # Next instruction depends on previous register op
+    ori x1, x1, 0x1BC
+    nop # Next instruction depends on previous register op
+    sh x1, 100(x0)
+    lh x31, 100(x0)
+
+    lui x1, 0xF
+    nop # Next instruction depends on previous register op
+    ori x1, x1, 0x1BC
+    nop # Next instruction depends on previous register op
+    sh x1, 106(x0)
+    lh x31, 106(x0)

bench/tests/op/lhu.s

@@ -0,0 +1,16 @@
+# expected: 0000F1BC, 0000F1BC
+    .text
+_start:
+    lui x1, 0xF
+    nop # Next instruction depends on previous register op
+    ori x1, x1, 0x1BC
+    nop # Next instruction depends on previous register op
+    sh x1, 100(x0)
+    lhu x31, 100(x0)
+
+    lui x1, 0xF
+    nop # Next instruction depends on previous register op
+    ori x1, x1, 0x1BC
+    nop # Next instruction depends on previous register op
+    sh x1, 106(x0)
+    lhu x31, 106(x0)

bench/tests/op/lw.s

@@ -0,0 +1,9 @@
+# expected: 123451BC
+    .text
+_start:
+    lui x1, 0x12345
+    nop # Next instruction depends on previous register op
+    ori x1, x1, 0x1BC
+    nop # Next instruction depends on previous register op
+    sw x1, 100(x0)
+    lw x31, 100(x0)