Files
fmn_processor/bench/tests/op/lw.s

10 lines
238 B
ArmAsm

# expected: 123451BC
.text
_start:
lui x1, 0x12345
nop # Next instruction depends on previous register op
ori x1, x1, 0x1BC
nop # Next instruction depends on previous register op
sw x1, 100(x0)
lw x31, 100(x0)