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Rust: Color pub u8

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This commit is contained in:
Albin Chaboissier
2025-12-02 14:17:52 +01:00
parent d757633816
commit 54ec7106ed
5 changed files with 254 additions and 53 deletions
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2
bench/programs_rust/Cargo.toml
View File

@@ -1,6 +1,6 @@
[workspace]
resolver = "3"
members = ["fpga-lib", "fpga-lib-macros", "hello-rust"]
members = ["fpga-lib", "fpga-lib-macros", "hello-rust", "rot-cube"]
[profile.release]
panic = "abort"

77
bench/programs_rust/fpga-lib/src/vga.rs
View File

@@ -6,12 +6,10 @@ pub const HEIGHT: usize = 240;
#[repr(transparent)]
#[derive(Clone, Copy)]
pub struct Color(pub(crate) u8);
pub struct Color(pub u8);
impl Color
{
pub const fn from_rgb(r: u8, g: u8, b: u8) -> Self
{
impl Color {
pub const fn from_rgb(r: u8, g: u8, b: u8) -> Self {
Self(((r >> 6) << 6) | ((g >> 5) << 3) | (b >> 5))
}
}
@@ -26,12 +24,10 @@ pub const BLUE: Color = Color::from_rgb(0, 0, 255);
pub struct VGA {}
impl VGA
{
impl VGA {
/// # Safety
/// `x` must be less than `WIDTH` and `y` must be less than `HEIGHT`
pub unsafe fn write_pixel_unsafe(x: u16, y: u16, color: Color)
{
pub unsafe fn write_pixel_unsafe(x: u16, y: u16, color: Color) {
let pixel_index = x as usize + y as usize * WIDTH;
let word_index = pixel_index / 4; // Get index of the word in which the pixel is
let byte_index = pixel_index % 4; // Get index of the byte within the word for the pixel
@@ -41,14 +37,10 @@ impl VGA
/// # Safety
/// `x` must be less than `WIDTH` and `y` must be less than `HEIGHT`
pub unsafe fn draw_char(x: u16, y: u16, c: char, color: Color)
{
let c = if (c as u8 > b'~') || ((c as u8) < b' ')
{
pub unsafe fn draw_char(x: u16, y: u16, c: char, color: Color) {
let c = if (c as u8 > b'~') || ((c as u8) < b' ') {
b'/' - b' '
}
else
{
} else {
c as u8 - b' '
};
@@ -56,10 +48,8 @@ impl VGA
let char_x = (c as usize % 32) * FONT_WIDTH;
let char_y = (c as usize / 32) * FONT_HEIGHT;
for i in 0..(FONT_WIDTH as u16)
{
for j in 0..(FONT_HEIGHT as u16)
{
for i in 0..(FONT_WIDTH as u16) {
for j in 0..(FONT_HEIGHT as u16) {
let xx = x + i;
let yy = y + j;
@@ -73,14 +63,10 @@ impl VGA
}
}
pub unsafe fn draw_char_bg(x: u16, y: u16, c: char, color: Color, bg_color: Color)
{
let c = if (c as u8 > b'~') || ((c as u8) < b' ')
{
pub unsafe fn draw_char_bg(x: u16, y: u16, c: char, color: Color, bg_color: Color) {
let c = if (c as u8 > b'~') || ((c as u8) < b' ') {
b'/' - b' '
}
else
{
} else {
c as u8 - b' '
};
@@ -88,21 +74,15 @@ impl VGA
let char_x = (c as usize % 32) * FONT_WIDTH;
let char_y = (c as usize / 32) * FONT_HEIGHT;
for i in 0..(FONT_WIDTH as u16)
{
for j in 0..(FONT_HEIGHT as u16)
{
for i in 0..(FONT_WIDTH as u16) {
for j in 0..(FONT_HEIGHT as u16) {
let xx = x + i;
let yy = y + j;
if xx < (WIDTH as u16) && yy < (HEIGHT as u16)
{
if unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) }
{
if xx < (WIDTH as u16) && yy < (HEIGHT as u16) {
if unsafe { Self::font_plate_index(char_x as u16 + i, char_y as u16 + j) } {
unsafe { Self::write_pixel_unsafe(xx, yy, color) }
}
else
{
} else {
unsafe { Self::write_pixel_unsafe(xx, yy, bg_color) }
}
}
@@ -112,18 +92,15 @@ impl VGA
/// # Safety
/// The text must have a length that can fit within a `u16`
pub unsafe fn draw_string(x: u16, y: u16, str: &str, color: Color)
{
pub unsafe fn draw_string(x: u16, y: u16, str: &str, color: Color) {
str.chars().enumerate().for_each(|(i, c)| unsafe {
Self::draw_char(x + i as u16 * (FONT_WIDTH as u16), y, c as char, color)
});
}
fn digit_count(mut val: u64) -> u64
{
fn digit_count(mut val: u64) -> u64 {
let mut i = 0;
while val != 0
{
while val != 0 {
val /= 10;
i += 1;
}
@@ -131,17 +108,14 @@ impl VGA
i
}
pub unsafe fn draw_u64(x: u16, y: u16, mut val: u64, color: Color, bg_color: Color)
{
if val == 0
{
pub unsafe fn draw_u64(x: u16, y: u16, mut val: u64, color: Color, bg_color: Color) {
if val == 0 {
unsafe { Self::draw_char_bg(x, y, '0', color, bg_color) }
return;
}
let digit_count = Self::digit_count(val) - 1;
let mut i = digit_count as u16;
while val != 0
{
while val != 0 {
let digit = val % 10;
val /= 10;
@@ -160,8 +134,7 @@ impl VGA
}
}
unsafe fn font_plate_index(x: u16, y: u16) -> bool
{
unsafe fn font_plate_index(x: u16, y: u16) -> bool {
let pixel_index = (y as usize) * FONTPLATE_WIDTH + (x as usize);
let byte_index = pixel_index / 8;
let bit_index = pixel_index % 8;

8
bench/programs_rust/rot-cube/Cargo.toml Normal file
View File

@@ -0,0 +1,8 @@
[package]
name = "rot-cube"
version = "0.1.0"
edition = "2024"
[dependencies]
fpga-lib = { path = "../fpga-lib" }
libm = "0.2.11"

100
bench/programs_rust/rot-cube/src/main.rs Normal file
View File

@@ -0,0 +1,100 @@
#![no_std]
#![no_main]
use core::{
arch::asm,
ops::{Add, Mul, Sub},
};
use fpga_lib::{
interface::{Buttons, Leds},
panic_handler,
register::X31,
vga::{BLACK, BLUE, Color, FONT_WIDTH, GREEN, HEIGHT, RED, VGA, WHITE, WIDTH},
};
panic_handler! {}
pub struct Vec3(f32, f32, f32);
pub struct Mat3x3([[f32; 3]; 3]);
impl Mul<Mat3x3> for Mat3x3
{
type Output = Mat3x3;
fn mul(self, rhs: Mat3x3) -> Self::Output
{
Mat3x3([
[
rhs.0[0][0] * self.0[0][0],
rhs.0[0][1] * self.0[1][0],
rhs.0[0][2] * self.0[2][0],
],
[
rhs.0[1][0] * self.0[0][1],
rhs.0[1][1] * self.0[1][1],
rhs.0[1][2] * self.0[2][1],
],
[
rhs.0[2][0] * self.0[0][2],
rhs.0[2][1] * self.0[1][2],
rhs.0[2][2] * self.0[2][2],
],
])
}
}
impl Mul<Vec3> for Mat3x3
{
type Output = Vec3;
fn mul(self, rhs: Vec3) -> Self::Output
{
Vec3(
self.0[0][0] * rhs.0 + self.0[0][1] * rhs.1 + self.0[0][2] * rhs.2,
self.0[1][0] * rhs.0 + self.0[1][1] * rhs.1 + self.0[1][2] * rhs.2,
self.0[2][0] * rhs.0 + self.0[2][1] * rhs.1 + self.0[2][2] * rhs.2,
)
}
}
const CUBE: [Vec3; 8] = [
Vec3(1., 1., 1.),
Vec3(1., 1., -1.),
Vec3(1., -1., -1.),
Vec3(1., -1., 1.),
Vec3(-1., 1., 1.),
Vec3(-1., 1., -1.),
Vec3(-1., -1., -1.),
Vec3(-1., -1., 1.),
];
#[rustfmt::skip]
const LINES: [usize; 24] = [
// Face 1
0, 1,
1, 2,
2, 3,
3, 0,
// Face 2
4, 5,
5, 6,
6, 7,
7, 4,
// Cross faces
0, 4,
1, 5,
2, 6,
3, 7
];
#[unsafe(no_mangle)]
pub extern "C" fn main() -> !
{
loop
{
core::hint::spin_loop();
}
}

120
tight_setup_hold_pins.txt Normal file
View File

@@ -0,0 +1,120 @@
+====================+====================+============================================+
| Launch Setup Clock | Launch Hold Clock | Pin |
+====================+====================+============================================+
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[33]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[26]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[43]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[50]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[44]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[27]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[1]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[45]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[19]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[21]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[22]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[58]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[41]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[6]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[42]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[11]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[13]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[39]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[54]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[30]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[9]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[28]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[37]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[34]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[62]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[14]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[59]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[25]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[10]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[32]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[51]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | clnt/clintRegValue_reg[56]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[61]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[57]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[47]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[53]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[52]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[48]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[46]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[43]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[49]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[44]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[42]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[45]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[26]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[33]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[29]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[27]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[19]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[18]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[7]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/reg_pc_reg[4]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[51]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[47]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[43]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[40]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[39]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[34]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[30]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[24]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[125]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[122]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[22]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[20]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[107]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[124]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[12]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[102]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[101]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[10]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[116]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[117]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[6]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[94]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[114]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[106]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[109]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[99]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[104]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[112]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[120]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[93]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[97]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/cycles_remaining_reg[6]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[98]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[91]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[121]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[118]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_dividend_reg[1]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[95]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[87]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[88]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[85]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[100]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[92]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[86]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[84]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[64]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[83]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[96]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[67]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[74]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[68]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[90]/D |
| clk_out1_clk_wiz_0 | clk_out1_clk_wiz_0 | core/alu/divider/reg_divisor_reg[77]/D |
+--------------------+--------------------+--------------------------------------------+