Merge branch 'rv64i' of gitlab.ensimag.fr:thillarj/FMN_2526S1_thillarj_chaboisa into rv64i

src/main/scala/projet/ControlUnit.scala

@@ -54,7 +54,7 @@ class CUInterface extends Bundle {
     val mux_regpc_executepc = Output(Bool())
 
     // Selects pc adder or write back for pc write
-    val mux_pcadder_writeback = Output(Bool())
+    val mux_pcadder_jalrwriteback = Output(Bool())
 
     // Selects pc or write back for register write
     val mux_writeback_pc = Output(Bool())
@@ -137,7 +137,7 @@ class ControlUnit() extends Module {
     io.mux_incrpc4_imm := true.B;
     io.mux_regpc_executepc := true.B;
     io.mux_writeback_pc := true.B;
-    io.mux_pcadder_writeback := true.B;
+    io.mux_pcadder_jalrwriteback := true.B;
     io.mux_executeout_dout := true.B;
 
     // Decode instruction
@@ -175,7 +175,7 @@ class ControlUnit() extends Module {
             io.is_jump := true.B
             io.mux_incrpc4_imm := false.B; // Send the immediate in PC
             io.mux_regpc_executepc := false.B; // Add the immediate to the previous PC
-            io.mux_pcadder_writeback := true.B;
+            io.mux_pcadder_jalrwriteback := true.B;
             io.optype := OpType.J
         }
 
@@ -190,7 +190,7 @@ class ControlUnit() extends Module {
             io.mux_regb_imm := false.B; // Send imm to ALU B
 
             io.mux_alu_imm := true.B; // Send alu out to write back line
-            io.mux_pcadder_writeback := false.B; // Set pc to writeback dest
+            io.mux_pcadder_jalrwriteback := false.B; // Set pc to writeback dest
             io.optype := OpType.I
         }