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Update makefile to get more logs and flash using openFPGALoader

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This commit is contained in:
Julien THILLARD
2025-11-04 13:36:20 +01:00
parent ff440776bb
commit 2c77ed3bef
1 changed files with 15 additions and 25 deletions
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38
Makefile
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@@ -1,4 +1,5 @@
COMMON_DIR := common COMMON_DIR := common
FPGA_BOARD = zybo_z7_10
TOCLEAN = $(filter %log %.jou %.rpt %.mmi %.dcp %.csv\ TOCLEAN = $(filter %log %.jou %.rpt %.mmi %.dcp %.csv\
%.wdb vivado% updatemem% usage_statistics_webtalk%,$(wildcard *)) %.wdb vivado% updatemem% usage_statistics_webtalk%,$(wildcard *))
@@ -6,8 +7,6 @@ TOCLEAN += $(wildcard _*) .Xil out RTL build download.bit
# macro de verbosité # macro de verbosité
VERB := 0 VERB := 0
q = $(if $(filter 1, $(VERB)),$1,\
$(if $2,@echo $2 && $1 > $3 2>&1, @$1))
# macro de vérification de variables d'environnement # macro de vérification de variables d'environnement
check_vars = $(foreach v, $1, $(if $(filter undefined, $(origin $v)),\ check_vars = $(foreach v, $1, $(if $(filter undefined, $(origin $v)),\
@@ -61,17 +60,13 @@ compile: $(MEM)
$(MEM_DIR): $(MEM_DIR):
@mkdir -p $@ @mkdir -p $@
$(MEM_DIR)/crt.o: $(BENCH_DIR)/crt.S |$(MEM_DIR) $(MEM_DIR)/crt.o: $(BENCH_DIR)/crt.S |$(MEM_DIR)
$(call q,\ $(CC) $(CFLAGS) -c $< -o $@
$(CC) $(CFLAGS) -c $< -o $@ , " Compilation crt",$@.log)
$(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o|$(MEM_DIR) $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o|$(MEM_DIR)
$(call q,\ $(CC) $(ELFFLAGS) $< -o $@
$(CC) $(ELFFLAGS) $< -o $@ , " Compilation $<",$@.log)
$(MEM_DIR)/%.elf: $(BENCH_DIR)/%.s |$(MEM_DIR) $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.s |$(MEM_DIR)
$(call q,\ $(CC) $(CFLAGS) -o $@ $<
$(CC) $(CFLAGS) -o $@ $<, " Compilation $<",$@.log)
$(MEM_DIR)/%.mem: $(MEM_DIR)/%.elf |$(MEM_DIR) $(MEM_DIR)/%.mem: $(MEM_DIR)/%.elf |$(MEM_DIR)
$(call q,\ $(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk
$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk," Génération de $@",$@)
############################################################################### ###############################################################################
@@ -127,14 +122,11 @@ PROG_HASH := $(shell echo "$(PROG)" | md5sum | cut -d' ' -f1)
RTL: $(SRC_SV) ##! Génération du SystemVerilog RTL: $(SRC_SV) ##! Génération du SystemVerilog
$(SRC_SV): mill $(SRC) $(SRC_SV): mill $(SRC)
$(call q, ./mill TPchisel.runMain common.EmitModule $(TOP_REP).$(TOP) $(PARAM) \ ./mill TPchisel.runMain common.EmitModule $(TOP_REP).$(TOP) $(PARAM)
, " Génération du SystemVerilog",/dev/null)
$(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt: $(COMMON_DIR)/synthese.vivado.tcl RTL $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt: $(COMMON_DIR)/synthese.vivado.tcl RTL
@$(call check_vars,XILINX_VIVADO) @$(call check_vars,XILINX_VIVADO)
$(call q, \ $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP)
$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP)\
, " Synthese",$@.log)
synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt ##! Réalise la synthèse grossière pour évaluer les performances synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt ##! Réalise la synthèse grossière pour évaluer les performances
@echo "Rapport d'utilisation disponible dans $(TOP)_utilization.rpt" @echo "Rapport d'utilisation disponible dans $(TOP)_utilization.rpt"
@@ -143,9 +135,7 @@ synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt ##! Réal
golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL
@$(call check_vars,XILINX_VIVADO PROG) @$(call check_vars,XILINX_VIVADO PROG)
$(call q, \ $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP) $@ $(MEM_FILE)
$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP) $@ $(MEM_FILE) \
, " Génération du bitstream",$@.log)
.prog_$(PROG_HASH): .prog_$(PROG_HASH):
@rm -f .prog_* # Supprimer les anciens marqueurs @rm -f .prog_* # Supprimer les anciens marqueurs
@@ -153,8 +143,7 @@ golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL
download.bit: golden.bit $(MEM_FILE) $(MMI_FILE) .prog_$(PROG_HASH) download.bit: golden.bit $(MEM_FILE) $(MMI_FILE) .prog_$(PROG_HASH)
@$(call check_vars,XILINX_VIVADO PROG) @$(call check_vars,XILINX_VIVADO PROG)
$(call q, $(XILINX_PREFIX)updatemem -debug -force --meminfo $(MMI_FILE) --data $(MEM_FILE) --proc $(MEM_ID) --bit $< --out $@\ $(XILINX_PREFIX)updatemem -debug -force --meminfo $(MMI_FILE) --data $(MEM_FILE) --proc $(MEM_ID) --bit $< --out $@
, " Mise à jour du fichier du bitstream", $@.mem.log)
check_usb: check_usb:
@lsusb | grep -q FT2232C || \ @lsusb | grep -q FT2232C || \
@@ -176,11 +165,12 @@ check_hw: check_usb check_driver
fpga: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw ##! Génére le fichier de configuration du FPGA et le programme fpga: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw ##! Génére le fichier de configuration du FPGA et le programme
@$(call check_vars,XILINX_VIVADO) @$(call check_vars,XILINX_VIVADO)
$(call q, \
$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $(COMMON_DIR)/programFPGA.vivado.tcl -nolog -nojournal \ $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $(COMMON_DIR)/programFPGA.vivado.tcl -nolog -nojournal \
-tclargs $< \ -tclargs $<
, " Programmation",prog.log )
flash: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw
openFPGALoader -b $(FPGA_BOARD) $<
##@ Nettoyage ##@ Nettoyage
clean: ##! Fais le nettoyage clean: ##! Fais le nettoyage
$(call q, rm -rf $(TOCLEAN),) rm -rf $(TOCLEAN)