From 2c77ed3bef8e3dbaab36031da1f1d76715d8582d Mon Sep 17 00:00:00 2001
From: supersurviveur <julien.thillard38@gmail.com>
Date: Tue, 4 Nov 2025 13:36:20 +0100
Subject: [PATCH] Update makefile to get more logs and flash using
 openFPGALoader

---
 Makefile | 40 +++++++++++++++-------------------------
 1 file changed, 15 insertions(+), 25 deletions(-)

diff --git a/Makefile b/Makefile
index 4c68c9d..f200dca 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,5 @@
 COMMON_DIR  := common
+FPGA_BOARD = zybo_z7_10
 
 TOCLEAN = $(filter %log %.jou %.rpt %.mmi %.dcp %.csv\
                    %.wdb vivado% updatemem% usage_statistics_webtalk%,$(wildcard *))
@@ -6,8 +7,6 @@ TOCLEAN += $(wildcard _*) .Xil out RTL build download.bit
 
 # macro de verbosité
 VERB     := 0
-q         = $(if $(filter 1, $(VERB)),$1,\
-				$(if $2,@echo $2 && $1 > $3 2>&1, @$1))
 
 # macro de vérification de variables d'environnement
 check_vars = $(foreach v, $1, $(if $(filter undefined, $(origin $v)),\
@@ -61,17 +60,13 @@ compile: $(MEM)
 $(MEM_DIR):
 	@mkdir -p $@
 $(MEM_DIR)/crt.o: $(BENCH_DIR)/crt.S |$(MEM_DIR)
-	$(call q,\
-	$(CC) $(CFLAGS) -c $< -o $@ , "  Compilation crt",$@.log)
+	$(CC) $(CFLAGS) -c $< -o $@
 $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.c $(MEM_DIR)/crt.o|$(MEM_DIR)
-	$(call q,\
-	$(CC) $(ELFFLAGS) $< -o $@ , "  Compilation $<",$@.log)
+	$(CC) $(ELFFLAGS) $< -o $@
 $(MEM_DIR)/%.elf: $(BENCH_DIR)/%.s |$(MEM_DIR)
-	$(call q,\
-	$(CC) $(CFLAGS) -o $@ $<, "  Compilation $<",$@.log)
+	$(CC) $(CFLAGS) -o $@ $<
 $(MEM_DIR)/%.mem: $(MEM_DIR)/%.elf |$(MEM_DIR) 
-	$(call q,\
-	$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk,"  Génération de $@",$@)
+	$(OBJDUMP) $(ODFLAGS) $< | awk -f $(OBTOMEM) | awk -f common/fix_mem.awk
 
 
 ###############################################################################
@@ -127,14 +122,11 @@ PROG_HASH := $(shell echo "$(PROG)" | md5sum | cut -d' ' -f1)
 RTL: $(SRC_SV) ##! Génération du SystemVerilog
 
 $(SRC_SV): mill $(SRC) 
-	$(call q, ./mill TPchisel.runMain common.EmitModule $(TOP_REP).$(TOP) $(PARAM) \
-	, "  Génération du SystemVerilog",/dev/null)
+	./mill TPchisel.runMain common.EmitModule $(TOP_REP).$(TOP) $(PARAM)
 
 $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt: $(COMMON_DIR)/synthese.vivado.tcl RTL 
 	@$(call check_vars,XILINX_VIVADO)
-	$(call q, \
-	    $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP)\
-	    , "  Synthese",$@.log)
+	$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP)
 
 synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt  ##! Réalise la synthèse grossière pour évaluer les performances
 	@echo "Rapport d'utilisation disponible dans $(TOP)_utilization.rpt"
@@ -143,9 +135,7 @@ synthese: $(TOP)_utilization.rpt $(TOP)_timing.rpt $(TOP)_summary.rpt  ##! Réal
 
 golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL
 	@$(call check_vars,XILINX_VIVADO PROG)
-	$(call q, \
-	    $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP) $@ $(MEM_FILE) \
-	    , "  Génération du bitstream",$@.log)
+	$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $< -tclargs $(FPGA) $(TOP) $(TOP_REP) $@ $(MEM_FILE)
 
 .prog_$(PROG_HASH):
 	@rm -f .prog_*  # Supprimer les anciens marqueurs
@@ -153,8 +143,7 @@ golden.bit: $(COMMON_DIR)/bitstream.vivado.tcl $(COMMON_DIR)/$(TOP).xdc RTL
 
 download.bit: golden.bit $(MEM_FILE) $(MMI_FILE) .prog_$(PROG_HASH)
 	@$(call check_vars,XILINX_VIVADO PROG)
-	$(call q, $(XILINX_PREFIX)updatemem -debug -force --meminfo $(MMI_FILE) --data $(MEM_FILE) --proc $(MEM_ID) --bit $< --out $@\
-	    , "  Mise à jour du fichier du bitstream", $@.mem.log)
+	$(XILINX_PREFIX)updatemem -debug -force --meminfo $(MMI_FILE) --data $(MEM_FILE) --proc $(MEM_ID) --bit $< --out $@	    
 
 check_usb:
 	@lsusb | grep -q FT2232C || \
@@ -176,11 +165,12 @@ check_hw: check_usb check_driver
 
 fpga: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw ##! Génére le fichier de configuration du FPGA et le programme
 	@$(call check_vars,XILINX_VIVADO)
-	$(call q, \
-	    $(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $(COMMON_DIR)/programFPGA.vivado.tcl -nolog -nojournal \
-	                           -tclargs $< \
-	    , "  Programmation",prog.log )
+	$(XILINX_PREFIX)vivado -nolog -nojournal -mode batch -source $(COMMON_DIR)/programFPGA.vivado.tcl -nolog -nojournal \
+	                           -tclargs $<
+
+flash: download.bit $(COMMON_DIR)/programFPGA.vivado.tcl check_hw
+	openFPGALoader -b $(FPGA_BOARD) $<
 
 ##@ Nettoyage
 clean: ##! Fais le nettoyage
-	$(call q, rm -rf $(TOCLEAN),) 
+	rm -rf $(TOCLEAN)