Adds addiw instruction, all tests passing

src/main/scala/projet/Rv64i.scala

@@ -30,6 +30,7 @@ class Rv64i(sim: Boolean = true) extends Module {
     dmem.io.sign_extend := control_unit.io.memory_sign_extend
 
     control_unit.io.alu_comp_result := alu.io.comp_result
+    alu.io.word_mode := control_unit.io.alu_word_mode
 
     // PC delayed to execute stage for auipc op
     val execute_pc = Delay.Delay(reg_pc, 1, 0.U);