Adds addiw instruction, all tests passing

src/main/scala/projet/ControlUnit.scala

@@ -8,8 +8,11 @@ class CUInterface extends Bundle {
     val instruction = Input(UInt(32.W))
     val reg_file_we = Output(Bool())
     val alu_opcode = Output(AluOpCode())
+
+    // TODO: Maybe bundle alu <> cu
     // Alu comparison result
     val alu_comp_result = Input(Bool())
+    val alu_word_mode = Output(Bool())
 
     val optype = Output(OpType())
 
@@ -95,6 +98,9 @@ object OpCode extends ChiselEnum {
 
     // Type I
     val OpLoad = "b0000011".U
+
+    // ~~ Rv64i ~~
+    val OpImmW = "b0011011".U
 }
 
 class ControlUnit() extends Module {
@@ -102,6 +108,7 @@ class ControlUnit() extends Module {
 
     io.reg_file_we := false.B
     io.alu_opcode := AluOpCode.Add
+    io.alu_word_mode := false.B
     io.optype := OpType.U
     io.is_jump := false.B;
     io.memory_size := DMemSize.Word
@@ -196,6 +203,12 @@ class ControlUnit() extends Module {
             io.optype := OpType.I
             opLoad(funct3, io);
         }
+
+        is(OpCode.OpImmW) {
+            io.reg_file_we := true.B // Write to regfile
+            io.optype := OpType.I
+            opImmW(funct3, funct7, io);
+        }
     }
 
     // Implements functions for all instruction of the opImm kind
@@ -224,6 +237,7 @@ class ControlUnit() extends Module {
         io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
         io.mux_alu_imm := true.B;
         io.mux_rega_pc := true.B;
+        io.alu_word_mode := false.B;
         switch(funct3) {
             // Type I
             is(Funct3.ADDI) {
@@ -505,4 +519,40 @@ class ControlUnit() extends Module {
             }
         }
     }
+
+    // ~~~ EXTENSIONS ~~~
+
+    // ~~ Rv64i ~~
+
+    // Implements functions for all instruction of the opImm, w  kind
+    def opImmW(funct3: UInt, funct7: UInt, io: CUInterface) = {
+        // Meaning of Funct3 in the context of an OpImm instruction
+        val _ = funct7;
+        object Funct3 extends ChiselEnum {
+            // Type I
+            val ADDIW = "b000".U
+            val SLLIW = "b001".U
+
+            // Unimplemented
+            val SRLIW_SRAIW = "b101".U // Right shifts
+        }
+
+        // Meaning of Funct7 in the context of SHIFTR IR instructions
+        // object IRFunct7 extends ChiselEnum {
+        //     val SRLI = "b0000000".U
+        //     val SRAI = "b0100000".U
+        // }
+
+        io.mux_regb_imm := false.B; // OpImm are operations with imm, so send imm to ALU
+        io.mux_alu_imm := true.B;
+        io.mux_rega_pc := true.B;
+        switch(funct3) {
+            // Type I
+            is(Funct3.ADDIW) {
+                io.alu_word_mode := true.B
+                io.alu_opcode := AluOpCode.Add
+                io.optype := OpType.I
+            }
+        }
+    }
 }