Adds addiw instruction, all tests passing

src/main/scala/projet/Alu.scala

@@ -5,9 +5,9 @@ import chisel3.util.switch
 import chisel3.util.is
 
 object AluOpCode extends ChiselEnum {
-    val Add, AddW, Sub, And, Or, Xor, ShiftLeft, ShiftRight,
-        ShiftArithmeticRight, LessThanSigned, LessThanUnsigned,
-        GreaterEqualSigned, GreaterEqualUnsigned, Equal = Value
+    val Add, Sub, And, Or, Xor, ShiftLeft, ShiftRight, ShiftArithmeticRight,
+        LessThanSigned, LessThanUnsigned, GreaterEqualSigned,
+        GreaterEqualUnsigned, Equal = Value
 }
 
 class Alu extends Module {
@@ -19,65 +19,87 @@ class Alu extends Module {
         val out = Output(UInt(64.W))
         val opcode = Input(AluOpCode())
         val comp_result = Output(Bool())
+
+        // ~~ Rv64i ~~
+        // If word_mode is enabled, operations are performed
+        // on 32-bit-truncated inputs and then sign extended to 64bits
+        val word_mode = Input(Bool())
     })
 
     io.out := 0.U;
     io.comp_result := false.B;
+    val out = WireInit(0.U(64.W))
+    val op_a = WireInit(0.U(64.W))
+    val op_b = WireInit(0.U(64.W))
+
+    // Defaults
+    op_a := io.a
+    op_b := io.b
+    io.out := out
+
+    // Truncate operands, sext result
+    when(io.word_mode) {
+        op_a := io.a(31, 0)
+        op_b := io.b(31, 0)
+
+        io.out := SignExtend.Sext(out(31, 0), 64)
+    }
+
     switch(io.opcode) {
         is(Add) {
-            io.out := io.a + io.b;
+            out := io.a + io.b;
         }
 
         is(Sub) {
-            io.out := io.a - io.b;
+            out := io.a - io.b;
         }
 
         is(And) {
-            io.out := io.a & io.b;
+            out := io.a & io.b;
         }
 
         is(Or) {
-            io.out := io.a | io.b;
+            out := io.a | io.b;
         }
 
         is(Xor) {
-            io.out := io.a ^ io.b;
+            out := io.a ^ io.b;
         }
 
         is(ShiftLeft) {
-            io.out := io.a << io.b(5, 0);
+            out := io.a << io.b(5, 0);
         }
 
         is(ShiftRight) {
-            io.out := io.a >> io.b(5, 0);
+            out := io.a >> io.b(5, 0);
         }
 
         is(ShiftArithmeticRight) {
             // >> means arithmetic shift for SInts
-            io.out := (io.a.asSInt >> io.b(5, 0)).asUInt;
+            out := (io.a.asSInt >> io.b(5, 0)).asUInt;
         }
 
         is(LessThanUnsigned) {
             val less_than = io.a < io.b;
-            io.out := less_than;
+            out := less_than;
             io.comp_result := less_than;
         }
 
         is(LessThanSigned) {
             val less_than = io.a.asSInt < io.b.asSInt
-            io.out := less_than
+            out := less_than
             io.comp_result := less_than;
         }
 
         is(GreaterEqualUnsigned) {
             val geq_than = io.a >= io.b;
-            io.out := geq_than
+            out := geq_than
             io.comp_result := geq_than;
         }
 
         is(GreaterEqualSigned) {
             val geq_than = io.a.asSInt >= io.b.asSInt
-            io.out := geq_than
+            out := geq_than
             io.comp_result := geq_than;
         }