Stage 6: implementation, untested

2025-11-06 16:18:01 +01:00
parent 1462563e39
commit 2779471523
9 changed files with 180 additions and 32 deletions
--- a/src/main/scala/projet/Rv32i.scala
+++ b/src/main/scala/projet/Rv32i.scala
@@ -17,7 +17,11 @@ class Rv32i(sim: Boolean = true) extends Module {
    reg_file.io.rd_data := 0.U;
    io.x31 := reg_file.io.x31
    if (sim) {
-        io.valid_x31.get := reg_file.io.valid_x31.get && Delay.Delay(!reset.asBool, 1, false.B)
+        io.valid_x31.get := reg_file.io.valid_x31.get && Delay.Delay(
+            !reset.asBool,
+            1,
+            false.B
+        )
    }

    val alu = Module(new Alu());