Writes reg(31) on x31 when running on the board

2025-11-09 19:47:05 +01:00
parent 441f665d34
commit 15d9707571
1 changed files with 8 additions and 6 deletions
--- a/src/main/scala/projet/RegFile.scala
+++ b/src/main/scala/projet/RegFile.scala
@@ -34,7 +34,6 @@ class RegFile(sim: Boolean = false) extends Module {
    // Simulation stuff
    if (sim) {
        io.valid_x31.get := false.B
-    }
        io.x31 := "hDEADC0DE".U
        when(io.we && io.rd_addr === 31.U) {
            io.x31 := io.rd_data
@@ -42,4 +41,7 @@ class RegFile(sim: Boolean = false) extends Module {
                io.valid_x31.get := true.B
            }
        }
+    } else {
+        io.x31 := regs(31.U)
+    }
 }