From 15d97075712fd7ed44fe8547cb0eed71872109fb Mon Sep 17 00:00:00 2001
From: supersurviveur <julien.thillard38@gmail.com>
Date: Sun, 9 Nov 2025 19:47:05 +0100
Subject: [PATCH] Writes reg(31) on x31 when running on the board

---
 src/main/scala/projet/RegFile.scala | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/main/scala/projet/RegFile.scala b/src/main/scala/projet/RegFile.scala
index 3a7354c..967b700 100644
--- a/src/main/scala/projet/RegFile.scala
+++ b/src/main/scala/projet/RegFile.scala
@@ -34,12 +34,14 @@ class RegFile(sim: Boolean = false) extends Module {
     // Simulation stuff
     if (sim) {
         io.valid_x31.get := false.B
-    }
-    io.x31 := "hDEADC0DE".U
-    when(io.we && io.rd_addr === 31.U) {
-        io.x31 := io.rd_data
-        if (sim) {
-            io.valid_x31.get := true.B
+        io.x31 := "hDEADC0DE".U
+        when(io.we && io.rd_addr === 31.U) {
+            io.x31 := io.rd_data
+            if (sim) {
+                io.valid_x31.get := true.B
+            }
         }
+    } else {
+        io.x31 := regs(31.U)
     }
 }